LMX2581: Question About Lock Detect Output Functionality based on LD_SELECT

Hello Charles,

Charles Luke said:

For values of LD_SELECT from 5 through 15, what is the format of the output in those cases? I assume 5 through 8 have to be clocked out to read a number while 9 through 15 are a simple logic output? Can you share what the format of each of these will be?

I believe you are misunderstanding how to use the LD_SELECT pin.

Basically, for register R7[12:8] (which determines LD_SELECT), you write the binary number for the LD_SELECT pin to behave in a specific way/output a state of the LMX2581. For instance, when looking at the table below, if you would want to divide the PLL_N value by two, you would set R7[12:8] = 00101 (or 5 in decimal/the first column on the table). This state could lead for the LMX2581 PLL_N to be half of its previous value. So, to directly answer your question, I don't believe a number would be outputted, but instead the PLL_N would change value.

However, as you also stated above, you can program the LD_SELECT pin to just track and output a behavior of the LMX2581. For instance, if you would want to know if the calibration is running, you would set R7[12:8] = 01100 and the LD_SELECT pin would output a state rather than change something within the part (as demonstrated in the previous example)

Charles Luke said:

For logic detection functions I assume these outputs change with the state of the phase lock and once setup don't require further programming in the synth. These then just become a logic output that can be read by a processor.

Correct! Once you set up the LD_SELECT bits to "watch" a specific type of lock detect, the LMX2581 will demonstrate lock based on what you set the LD_SELECT pin to track.

If I misunderstood your question, please feel free to further clarify. Hope this helps,

Good Luck,

Andrea

Thanks for the clarification that the PLL_N settings apply that function directly to the dividers. So, the only readback of data is when LD_SELECT = 4, everything else uses the LD output as simple logic? What is the Analog Lock Detect when LD_SELECT = 9? I don't see any writeup in the data sheet for this. How does this differ from LD_SELECT 1, 2, or 3?

I also have some questions about reg 6. The recommended programming lists R6 as one of the registers to be programmed in 8.5.2 in the data sheet. Am I correct to assume that RD_DIAGNOSTICS[19:0] is only a read function and that it represents a don't care condition for the R6 write? I understand the RDADDR[3:0] matters on write when one of the select pins in reg 7 are set to 4. Then the RDADDR will select which register is read back (ID = 0). So how should the R6 values be programmed on the R6 write?

Am I correct to assume that RD_DIAGNOSTICS[19:0] is only a read function and that it represents a don't care condition for the R6 write?