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CDCVF2505: About the calculation for optimizing the propagation delay

Ryoma Ohashi
Expert 5655 points
Part Number: CDCVF2505


Hi team

1. In the datasheet 10.2.2 Detailed Design Procedure, it says

"Determine the average output load seen by all clock outputs Y[3:0]."

for the first step of optimizing the propagation delay of the PLL.

In the case below,

1Y0=1Y1=4pF、1Y2=1Y3=0pF(not connected）

Is the average output load 4 pF or (4pF+4pF+0pF+0pF)/4=2pF?

2. For the average output load calculation, should we include the output capacitance of the device shown in the datasheet?

Regards,

Ohashi

  • +1
    TI__Genius 9260 points

    Hi Ohashi,

    We would include the output capacitance of the device in addition to external capacitor values. Lets say if you have 4pF and 1Y0 and 1Y1 and 0pF on 1Y2 and 1Y3, then the average output should be:  Average output load = (6.8 + 6.8 + 2.8 + 2.8) / 4 = 4.8 pF.

    Best,

    Asim