LMK04828: Why the PLL1 of LMK04828B can't lock?

Hi Andrea:

According to your suggestion, I change the loop filter as below figure.1 shown, but the LED for PLL1& PLL2 just blink one time quickly then light off , that mean PLL1 can't lock. My previous test also blink one time then light off. I also change Kpd from 1.25mA to 0.45mA but the same result is got.

CPOUT1 is measured, and it is 1.659V. Then I test 10MHz reference clock  at the location between AC-couple capacity and LMK04828B, it is OK as below figure.2 shown.

I attached the .tcs file. Could you please help me check it? Thanks in advance!

10M_TXCO_100M ex VCXO_bufferout.tcs

Figure.1

Figure.2

Best regards!

Jason

Hi， Andrea

Sorry, I can't get 2700nf and 0402 package capacity for C2. So I use the capacity and resistor close to these value in your suggestion.

Could you please help me confirm if the capacity and resistor in below figure are OK too?  By using these value, phase margin could reach 54.889deg which is great than 40 deg

Maybe there are another reason cause the unlock of PLL1?   

Best regards!

Jason

Hi， Andrea:

I change R and N, then make Fpd as 0.08MHz, and get below loop filter:C1=0.33nF, C2=22nF and R2=330kohm. I have these capacity and resistor in my hand. Phase margin reach to 74deg and jitter could reach to 26.34fs(Is this possible?) as below figure shown.

Could you please help me check if this loop filter is ok?   I have checked the circuit and electrical parameter  according to datasheet completely, and have no any idea about why PLL1 can't lock. This problem have troubled me ~one week

Thanks in advance!

Best Regards!

Jason

Hello Jason,

Can you connect the OSCout pin to your oscilloscope and send me a screenshot of it demonstrating the frequency that it's being outputted at?

Thanks,

Andrea

Hi， Andrea:

Figure1 is the 100MHz for OSCin(AC-couple and single-end), and Figure2 is the 100MHz for OSCout_P or _N(LVDS format I selected) under the condition of PLL1 unlock.  As below figure3 shown, my understanding is that OSCout is the buffered version of OSCin, so it is regardless of PLL1 lock or unlok, right?

Thanks in advance!

Figure1

Figure2

Figure3

Best Regards!

Jason

Hi， Andrea：

I updated loop filter component as very close to your above setup(C1=56nF,C2=2700nF and R2=2.2Kohm) as below figure1 shown, but  the PLL1 can't lock too. LED for PLL1 DLD  blink one time quickly then light off.  Then I use signal generator(KEYSIGHT E8257D) to output 10MHz into CLKin0 instead of CLKin1 from 10MHz TCXO, but the result is the same and LED for PLL1 DLD  blink one time quickly then light off. Figure2 is the 10MHz sine wave at the CLKin0. Once I switch LED for PLL2_DLD, it will light on after power on.

Through these  tests, maybe there are another reason cause PLL1 unlock? Have the VCXO not enough pull range to cover the frequency deviation? Please check the electrical parameter of 10M TXCO and VCXO on the first my post in this thread. This VCXO is used in TIDA-01021 and have frequency pull +/- 20ppm, so I use it on my board. I check the EVM of Xilinx(ZCU208) which use the VX-5014-EAE-3050-160M00 from Vectron as VCXO with the same 10MHz TCXO to supply clock for LMK04828B, as below figure3 shown. This VCXO have typ +/-90ppm tuning range which could lock the PLL1 and PLL2 on ZCU208.

Could you please duplicate the same setup as me in the TIDA-01021 for comparison? TIDA-01021 mainly use the LMK61E2 as source which skip the PLL2 and work under Single-PLL mode.

BTW, Merry Christmas to you! !!

Thanks in advance!

Figure1

Figure2

Figure3

Best Regards!

Jason

Hello Jason,

Unfortunately, I don't have access to the board you are describing or to the lab right now. However, I will test a similar setup in lab on the LMK04828EVM after the new year.

In the meantime, could you output try the following things:

1. Probe the CPout and the PLL1 DLD pins to your scope before, during and after programming the registers of the LMK04828 to see how the signal changes and send me a screenshot.

2. I want to check if PLL1 is in fact locked and outputting an incorrect state to the STATUD_LD pin. To do this, can you set PLL1 LD to PLL1 N and PLL2 LD to PLL1 R and route those two signals to two different channels in your scope and send me a screenshot of that.

3. Could you tell me how much jitter is being produced from your reference signal (the waveform you attached above is not enough)?

4. Attempt to lower window size to the other options (smaller window size). The data sheets recommends to lower window size when using a higher PFD, which is your case at 10 MHz.

Merry Christmas to you too!

Thanks,

Andrea

Hi， Andrea：

Many thanks for your time to response me!

About 4 suggestion, Please see below green word from me:

1. Probe the CPout and the PLL1 DLD pins to your scope before, during and after programming the registers of the LMK04828 to see how the signal changes and send me a screenshot.

[Jason]: I have one probe in my hand. I test CPout firstly.  After power on, CPout1 will be kept at ~1.65V as below figure shown. When no clock input to CLKin0 and CLKin1, CPout1 pin also will output ~1.65v which make VCXO output nominal value (100MHz). That will light LED for PLL2 on which mean PLL2 DLD lock

2. I want to check if PLL1 is in fact locked and outputting an incorrect state to the STATUD_LD pin. To do this, can you set PLL1 LD to PLL1 N and PLL2 LD to PLL1 R and route those two signals to two different channels in your scope and send me a screenshot of that.

[Jason]: I set STATUD_LD1 as PLL1 N and STATUD_LD2 as PLL1 R as below figure shown. After power on, PLL1 N and PLL1 R are high level(3.3v) too as below figure shown. They should be 10MHz signal(fpd), right? it is very strange. But output form DCLK2、SDCLK3、DCLK12 and SDCLK13 are normal

Could you please help check the. tcs file for me？.

10M_TXCO_100M ex VCXO_bufferout.tcs

                    PLL1 N                                                                                                 PLL1 R

3. Could you tell me how much jitter is being produced from your reference signal (the waveform you attached above is not enough)?

[Jason]: Now, I have no signal source analyzer or signal analyzer in my hand, so I only refer to the parameter in the datasheet:

This 10MHz TXCO also is used on the EVM of Xilinx(ZCU208)

4. Attempt to lower window size to the other options (smaller window size). The data sheets recommends to lower window size when using a higher PFD, which is your case at 10 MHz

[Jason]: I try to change window size from 43ns to 19ns or 9ns, but the PLL1 can't lock too.

It seems that no effect to reduce window size for 10MHz

Best regards!

Jason

Hi Jason,

Andrea is currently on Christmas holidays returning in the new year. I will try to look at your request in the next 2 days.

regards,

Julian

Hi, Julian and Andrea：

Are you back?

Thanks in advance!

Best regards!

Hello Jason,

I will try to get to this next week. Thank you for understanding.

Best,

Andrea

Hi, Andrea：

Sorry to disturb you again. Have you forgot this thread? 

Thanks in advance!

Best regards!

Jason

HI Jason,

Andrea is currently out of office. She will get back to you on this next week. Thanks for your patience.

Best,

Asim

Hello Jason,

Something to note from one of your answers is that PLL2 would be ON and PLL1 would be OFF if using the LMK04828 in single-PLL mode (you switched those two in your previous answer). So if you are waiting for PLL1 light to light up when in single-PLL mode, that will never occur because PLL2 is the only PLL being used and therefore achieving lock.

I have tested your setup on my board on my lab and I got both PLL1 and PLL2 to lock with the configuration you attached to one of your posts on this thread. Note that I changed a few values since I don't the same VCXO you have.

To answer the comments in green from above:

shen jie said:

That will light LED for PLL2 on which mean PLL2 DLD lock

From this statement and from the plot you gave, PLL2 is locking! So there should be no issues there.

shen jie said:

They should be 10MHz signal(fpd), right? it is very strange.

This is correct, it looks like your scope is measuring their voltage rather than their frequency. If you are probing the trace/test point and connecting it to the scope, that should have worked, maybe you need to set up your scope in a specific way?

shen jie said:

Could you please help check the. tcs file for me？

I checked it and after playing with a few files to match the configuration of my board, it should work! So your config should not be the problem here.

To move forward, could you either reinstate your problem with the most up to date .tcs file, PLL1 loop filter values, and PLL2 loop filter values, or create a brand new E2E post reinstate your most up-to-date problem if none of my comments above gave you an idea of what might be happening. Ideally, I would appreciate a new E2E post.

Best,

Andrea