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LMK61E2: Volatile Memory Protection

AlexWalton42
Expert 8335 points
Part Number: LMK61E2

 Hello,

Does the LMK61E2 have protection on the volatile memory against random I2C writes? If so, can you please point to the documentation explaining how it works and how to enable it.

Thanks in advance.

  • 0
    TI__Mastermind 22210 points

    Hello,

    I will investigate this and get back to you as soon as possible.

    Thanks,

    Kadeem

  • 0 in reply to Kadeem Samuel
    TI__Mastermind 22210 points

    Alexander,

    With regard to writing to the SRAM and EE, there are features described in the datasheet that would prove difficult to perform accidentally.

    For writing to the SRAM, the SRAM address would be written to R51, with the data written in the same transaction to R53. SRAM access terminates if a new transaction is started.

    For writing to the EEPROM, the SRAM contents are first written, after which 0xBE has to be written to R56 as an unlock to the EEPROM. Only after the R56 unlock is performed can a 1 be written to R49 to program the SRAM contents into the EEPROM.

    The functionality described above for both the SRAM and EEPROM is always enabled.

    Thanks,

    Kadeem