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LMK04828: Output clock issue

Part Number: LMK04828


Hi,

We are using LMK04828 clock synthesizer. Please find the attached schematic snapshot along with the tics pro clock file we're using.

1) We're unable to get following o/p clocks. Even though it looks like it's enabled in GUI.

SDCLKOUT1_P 7.68 MHz
SDCLKOUT5_P 7.68MHz
SDCLKOUT3_P/SDCLKOUT3_N 7.68MHz

2) Also we couldn't configure all the required clocks. Our requirement is as follows:-

DCLKOUT0_P/DCLKOUT0_N  245.76 MHz
SDCLKOUT1_P 7.68 MHz
DCLKOUT4_P/DCLKOUT4_N 245.76 MHz
SDCLKOUT5_P 7.68 MHz
DCLKOUT8_P/DCLKOUT8_N 100 MHz
SDCLKOUT9_P/SDCLKOUT9_N 27 MHz
DCLKOUT10_P/DCLKOUT10_N 52 MHz
SDCLKOUT11_P/SDCLKOUT11_N 125 MHz
SDCLKOUT3_P/SDCLKOUT3_N 7.68MHz

LMK04828_156.25MCLKin0_122.88MVCXO_245.76MDCLK_7.68MSYSREF.zip

  • Hello Abhishek,

    We will get back to you tomorrow as today is a holiday in the United States. Thank you for understanding.

    Best,

    Andrea

  • Hello Abhishek,

    It is not possible to generate those six different frequencies with one LMK04828. Instead you would either need two LMK04828 or another device that has two PLLs integrated in it, such as a clock gen or a DPLL. Therefore, to recommend the best device for your application, do you require the SYSREF functionality? Thanks!

    Best,

    Andrea

  • Can you answer 1 and 2 separately. I'm confused as to why clocks mentioned in point 1. is not generated, GUI shows 7.68 for those clocks

  • Hello Abhishek,

    1) We're unable to get following o/p clocks. Even though it looks like it's enabled in GUI.

    In order for the device to operate properly and output your desired waveforms, the PLL needs to lock. To do that the VCO needs to operate between the frequency ranges specified. Based on your config, you are attempting to operate the VCO at 2457.6 MHz, when VCO0 can only accept frequencies between 2495 MHz and 2705 MHz.

    2) Also we couldn't configure all the required clocks. Our requirement is as follows:

    I have used the tool Clock Tree Architect to generate different options of a clock tree that would work for your application. Depending on your space constraints, SYSREF/JESD204B requirements, output and input types, power, and jitter requirements, I can suggest a solution. I have included the results I got below, but feel free to use the tool yourself to determine the best clock tree for you.

    Hope this helps!

    Good luck,

    Andrea