LMK04828: LMK04828

Hello Sothea,

Can you also please provide the output frequencies and their types so that I can generate a config for you? Also, what VCXO frequency and what VCXO are you planning to use?

Regarding our lowest possible jitter device for jitter cleaners, I would recommend LMK04832 since it has better performance than the LMK04828. However, if you are looking for a network synchronizer/DPLL, then you would have to look at those devices here. Also, do you have a spec of what performance you are looking for?

Thanks,

Andrea

Hi Andrea,

No network is required in my application. I have total of 3 x ADC12DJ3200 on board, JESD204B is part of the deal

Here are the list of clocks outputs I can see

                Main input clk = 106.25Mhz

1. ADC1(sample clk) = 2.125Ghz;  LVDS or LVPECL
2. Sysref1 Clk = 3.3203125Mhz;    LVDS or LVPECL
3. ADC2(sample clk) = 2.125Ghz;  LVDS or LVPECL
4. Sysref2 Clk = 3.3203125Mhz;    LVDS or LVPECL
5. ADC3(sample clk) = 2.125Ghz;  LVDS or LVPECL
6. Sysref2 Clk = 3.3203125Mhz;    LVDS or LVPECL
7. CLK JESD204B = 212.5 Mhz;
8. FPGA REF CLK = 3.3203125 Mhz;
9. Optical XCVR CLK = 212.5 Mhz;

Requirements:  -156dbc/Hz noise floor ;  less than 100fs RMS jitter

LMk04832 is good if you recommended

Note all of these clocks are multiple of input clock 106.25Mhz

Please recommend a VCXO that would provide the lowest noise spectrum for that particular frequency