• State TI Thinks Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 3 answers
  • Subscribers 21 subscribers
  • Views 628 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CDCDB400: SMB Active

Darren Wetherhold
Prodigy 10 points
Part Number: CDCDB400

What is the minimum time required from CKPWRGD_PD# asserted HIGH to SMB become available for access?

  • 0
    TI__Genius 9260 points

    Hi Darren,

    I will look for this information and provide an update by Friday.

    Best,

    Asim

  • 0 in reply to Asim Khan
    TI__Genius 9260 points

    Hi Darren, 

    I was able to get more information about your query. SMBus interface gets enabled as soon as the CKPWRGD_PD#  is asserted HIGH but the response can depend on multiple things. 

    First thing to consider if this is a cold or warm start since cold-starts take longer than warm-starts as there are additional delay for circuit to fully power up and EEPROM is loaded into register which adds up into this delay. For warm-starts this additional delay doesn't occur.

    Next thing to consider is when the CKPWRGD_PD#  is asserted with respect to supply power. If CKPWRGD_PD#  is applied immediately after supply ramp then we have to consider cold-starts delay and EEPROM loading. While if CKPWRGD_PD# is asserted considerable amount of time after supply is established, EEPROM and cold start delay would be finished already so you would get a faster response.

    For precise timing, we need to know the actual use case scenario because its also depended on input frequency. But in general case, we can expect 300 us for cold-starts case as described above and 20us for warm-starts.


    Best,

    Asim 

  • 0 in reply to Asim Khan
    Prodigy 10 points

    Hi Asim,

    Thank you for the info.  Couple more follow on questions:

    1. What is the worst case delay time for internal EEPROM get loaded from power up, regardless of CKPWRGD_PD# being asserted or not? Please quantify by microseconds.
    2. Which input frequency are you referring to in your statement: "For precise timing, we need to know the actual use case scenario because its also depended on input frequency." Is it SMBCLK frequency or CLKIN_P/N  frequency?
    3. Why is timing dependent on external clock frequency?
    4. Does the internal EEPROM loading process require SMBCLK or CLKIN_P/N to run?

    Thanks,
    Darren

  • 0 in reply to Darren Wetherhold
    TI__Genius 9260 points

    Hi Darren,

    Darren Wetherhold said:
    What is the worst case delay time for internal EEPROM get loaded from power up, regardless of CKPWRGD_PD# being asserted or not? Please quantify by microseconds.

    Let me find this number for you since we have to run a simulation for this.

    Darren Wetherhold said:
    Why is timing dependent on external clock frequency?

    When power is applied to the device, and when the CKPWRGD_PD# pin is set HIGH, different parts of the power-up sequence are triggered. The power-up sequence consists of 4 timers + EEPROM data transfer. The first two counters + EEPROM data transfer run on the on-chip "boot oscillator", which can vary in frequency. The last two counters run on the input clock (CLKIN_P/N), which also varies in frequency. Nothing depends on the SMBCLK. So to summarize, EEPROM data transfer duration (and also the duration of the first two counters) increases with decreasing boot oscillator frequency, and the duration of the final two counters increases with decreasing input clock frequency.

    Darren Wetherhold said:
    Which input frequency are you referring to in your statement: "For precise timing, we need to know the actual use case scenario because its also depended on input frequency." Is it SMBCLK frequency or CLKIN_P/N  frequency?

    I am referring to CLKIN_P/N frequency.

    Darren Wetherhold said:
    Does the internal EEPROM loading process require SMBCLK or CLKIN_P/N to run?

    This doesn't require the SMBCLK or CLKIN to be running but I will confirm this and get back to you.


    Best,

    Asim

  • 0 in reply to Asim Khan
    TI__Genius 9260 points

    Hi Darren,

    Asim Khan said:
    Darren Wetherhold said:
    What is the worst case delay time for internal EEPROM get loaded from power up, regardless of CKPWRGD_PD# being asserted or not? Please quantify by microseconds.

    Let me find this number for you since we have to run a simulation for this.

    I was able to find the EEPROM worst case loading time. Its 210us from power being applied.

    Asim Khan said:
    Darren Wetherhold said:
    Which input frequency are you referring to in your statement: "For precise timing, we need to know the actual use case scenario because its also depended on input frequency." Is it SMBCLK frequency or CLKIN_P/N  frequency?

    I am referring to CLKIN_P/N frequency.

    This includes 'On chip boot oscillator' and 'CLKIN_P/N' frequency but CLKIN_P/N have less time contribution in this delay. Most of it is dependent on EEPROM loading + first two counter (depends on boot oscillator frequency). 

    Let me know if you need any further questions. 

    Best,

    Asim

  • 0 in reply to Asim Khan
    Prodigy 10 points

    Thank you Asim.

    Since two timers are CLKIN_P/N dependent, does it mean that the silicon is not accessible from SMBus without a clock present on CLKIN_P/N?

    Thanks,

    Darren

  • 0 in reply to Darren Wetherhold
    TI__Genius 9260 points
    Asim Khan said:
    For precise timing, we need to know the actual use case scenario because its also depended on input frequency.

    Let me correct my statement here. This would be boot chip oscillator frequency. CLKIN_P/N frequency is for last two counter which are used for controlled switchover of the digital logic from the boot oscillator to the input clock. If  CLKIN_P/N is not present this switchover won't happen.  These counter doesn't have any effect on SMBus availability. 

    Delay required to enable SMBus is mostly driven by EEPROM loading and first two counter. 

    I hope this clarifies it. Could you help share why this precise timing requirement is needed?

    Best,

    Asim