• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 3 answers
  • Subscribers 21 subscribers
  • Views 1030 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK04828: SYSREF Pulser Issue

KLN
Intellectual 320 points
Part Number: LMK04828

Hi / e2e.ti.com/.../4798065 

We have a LMK04828 based board, we are trying to achieve SYSREF Pulser at SYSREF Distribution path, 

Case1:

  • CLKIN0- 5MHz External Signal, 100MHz VCXO at OSCIN, SYSREF_MUX is set to SYSREF_Pulser (CLKIN0) 

We observe strange output at SYSREF Distribution path below is attached image of Captured waveform of SYSREF and Configuration files:

 

  • Multiple SYSREF and is non periodic output
  • SYSREF_Pulser count is 2 and We have tried checking SYSREF_PD set still we observe the same. 
  • We observe proper SYSREF when SYSREF_MUX is set to SYSREF Continuous but not on Pulser mode
  • We are not using SYNC Path. 

.

LMK Configuration file: 

Fullscreen secondary_lmk.txt Download 
R0 (INIT)	0x000090
R0	0x000004
R2	0x000200
R3	0x000306
R4	0x0004D0
R5	0x00055B
R6	0x000600
R12	0x000C51
R13	0x000D04
R256	0x01000A
R257	0x010155
R258	0x010255
R259	0x010301
R260	0x010422
R261	0x010500
R262	0x010670
R263	0x010755
R264	0x01086A
R265	0x010955
R266	0x010A55
R267	0x010BB1
R268	0x010C22
R269	0x010D00
R270	0x010E70
R271	0x010F11
R272	0x01106A
R273	0x011155
R274	0x011255
R275	0x0113B1
R276	0x011422
R277	0x011500
R278	0x011670
R279	0x011735
R280	0x01186A
R281	0x011955
R282	0x011A55
R283	0x011BB1
R284	0x011C22
R285	0x011D00
R286	0x011E71
R287	0x011F05
R288	0x01207E
R289	0x012155
R290	0x012255
R291	0x0123B1
R292	0x012422
R293	0x012500
R294	0x012670
R295	0x012755
R296	0x012808
R297	0x012955
R298	0x012A55
R299	0x012B00
R300	0x012C02
R301	0x012D00
R302	0x012EF9
R303	0x012F00
R304	0x013016
R305	0x013155
R306	0x013255
R307	0x013300
R308	0x013402
R309	0x013500
R310	0x0136F1
R311	0x013700
R312	0x013825
R313	0x013901
R314	0x013A00
R315	0x013B1E
R316	0x013C00
R317	0x013D0E
R318	0x013E03
R319	0x013F1B
R320	0x014009
R321	0x014100
R322	0x014200
R323	0x014350
R324	0x014400
R325	0x01457F
R326	0x014618
R327	0x014718
R328	0x014802
R329	0x014942
R330	0x014A02
R331	0x014B02
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015003
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x01540A
R341	0x015500
R342	0x01560A
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A64
R347	0x015BDC
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F0B
R352	0x016000
R353	0x016101
R354	0x016244
R355	0x016300
R356	0x016400
R357	0x01650F
R369	0x0171AA
R370	0x017202
R380	0x017C15
R381	0x017D33
R358	0x016600
R359	0x016700
R360	0x016801
R361	0x016959
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017300
R386	0x018200
R387	0x018300
R388	0x018400
R389	0x018500
R392	0x018800
R393	0x018900
R394	0x018A00
R395	0x018B00
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53

Please let us know, anything we are missing here.

Case2: We have observed the same thing with no input at CLKIN0 i.e. CLKIN0 is left open and with SYSREF_MUX set to SYSREF_Pulser.

  • 0
    TI__Genius 12560 points

    Hi,

    The SYSREF Pulser can be operate by external SYNC pin or SPI controlled (SYNC_MODE) and "SYSREF_MUX" needs to be "SYSREF_Pulser" mode

    Also the SYSREF_PLSR_PD bit should be low.

    In the current configuration, CLKin0 input re-clocking with SYSREF frequency and it continuously latching the SYSREF output.

    Please find below config file, which is updated for the SYSREF in pulser mode with SPI control. For SYSREF pulsed output, write the R318 register and it will generate the pulsed output.

    LMK04828_SYSREF_Pulser_e2e.tcs

     Thanks!

    Regards,

    Ajeet Pal

  • 0 in reply to Ajeet Pal
    Intellectual 320 points

    Hi Ajeet,
    Thanks for your response
    I apologise for presenting the issue to you incorrectly.

    We want to use our LMK04828 in reclocked mode, and the SYSREF to clkin0 is coming from outside.
    We want to reclock and send the incoming SYSREF through the SYSREF distribution mux.


    Based on our application, we want to send SYSREF as a pulsed and continuous signal via clKIN0.
    The issue is:

    When we configure the LMK in reclocked mode and do not feed any external input to CLKIn0, we see the PULSED waveform shown in the image.

    We shouldn't be getting anything because we're not feeding anything to clKin0.

  • 0 in reply to KLN
    TI__Genius 12560 points

    Hi,

    It seems, the both PLLs in dual PLL mode are locking with 0-delay mode and getting some SYSREF issue.

    Here, I have attached the latest config file. Please update the outputs based on requirement and see the re-clocked SYSREF performance.

    LMK04828_Reclocked_SYSREF_e2e.tcs

    Thanks!

    Regards,

    Ajeet Pal 

  • 0 in reply to Ajeet Pal
    Intellectual 320 points

    Hi ajeeth,

    Thanks for your configuration file
    we have tried bypassing vcxo and feeding clkin1 from external LMK
    We are using a giving SYSREF (pulsed or continuous) from an external LMK in this instance.


    At every SDClkouts output, we are seeing the same thing that is depicted in the image.

    pulse sysref is used for resting the NCO of multiple DACs which is creating a problem for us.
    request you to assist us in resolving the problem.

  • 0 in reply to KLN
    TI__Genius 12560 points

    Hi,

    This setup would required to meet the precise setup and hold timing. What is the CLKin1 frequency used in this configuration? If it is too high, then CLKin0 input delay need to adjusted enough to meet setup and hold timing.

    Otherwise, generate the SYSREF in secondary LMK and keep the CLKin0 reclocked with SYSREF frequency, it will have sufficient margin and should be improve the pulsed reclocked SYSREF outputs.

    Thanks!

    Regards,

    Ajeet Pal 

  • +1 in reply to Ajeet Pal
    Intellectual 320 points

    We noticed that the CLKIN0 input type was set to BIPOLAR for a sinewave input; changing it to MOS corrected the problem.