hello sir.
You want to enter it into LVCMOS_CLK of LMK00804B using 40MHz TCXO. For VDD and VDDO on the LMK, enter 3.3V.
My TCXO output range is 0.8Vp_p.
If you look at the datasheet, the VIL of LMK00804B is max 1.3V and VIH is min 2V, so it should not work.
However, the output has been confirmed to swing at 3V. I don't understand why you're doing this.
Please explain.
thanks
mr.lee
Hi Mr. Lee,
The input stage is similar to single ended input type. So you would see output gets enabled for smaller swing as well. If your swing is correctly following the VIL and VIH requirements in datasheet you would get the correct duty cycle on output otherwise you would run into duty cycle distortion. Ideally any thing below VIL value should stay low on output of buffer but this is not the case here due to input stage of this buffer.
Here is an example of how he VIL and VIH level can affect the duty cycle.
VIL = 1.25V
VIH = Around 2V
This case also gets triggered due to input structure similar to single ended input operation on differential buffer.
VIL = 0
VIH = 0.8V
This would cause duty cycle distortion.
Best.
Asim
