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LMK04828: Nested dual loop question

Cameron Wutzke
Expert 4037 points

Part Number: LMK04828

Hey all,

Question about simulating using PLLatinum tool. Tool only allows one PLL to be analyzed at a time, but we plan to use the nested dual loop zero delay mode

PLL1 will be narrowband (30Hz ) and the PLL2 will be broadband (100 KHz).  Can I safely assume that the I can estimate the loop behavior and phase margin of these two loops independently?  My thought is that the inner broadband loop shouldn’t affect the narrow outer loop, and vice versa.

Thank you!

  • +1
    TI__Mastermind 34270 points

    Hi Cameron,

    Yes, you can assume these behave independently. There is nothing special about the nesting operation that changes the phase noise characteristics of the system. Even though there is theoretically larger noise scaling from the PLL2 integrated VCO at PLL1 due to the larger N-divide, in practice the high-pass characteristic on the VCO noise coupled with the extremely low PLL1 loop bandwidth ensures this contribution is negligible overall compared to the typical cascading configuration.

    As a side note, in case you were unaware: you can model PLL1, export the phase noise of PLL1 using the Data Export -> Export Trace -> Phase Noise Total menu option, and then model PLL2 with the PLL1 phase noise trace used as the reference input:

    • Get PLL1 working how you want it and export the trace
    • While modeling PLL2, use either intermediate or advanced mode
    • Set PLL2 Fosc frequency to the correct VCXO frequency (this is essential for noise scaling)
    • On the phase noise tab, under the OSC, PLL, and VCO Noise group, within the input source noise selection, click "Load Data" and select the trace you exported from PLL1

    Note you could also use the load data option in PLL1 to model a reference input source, if you have a phase noise trace for it.

    Regards,

    Derek Payne

  • 0 in reply to Derek Payne
    TI__Expert 4037 points

    Hey Derek,

    Another question has come up concerning “hitless switching” and various Dual-Loop configurations.  We definitely need hitless switching, and would like to also have deterministic phase between input and output clocks.  It appears that deterministic phase is obtained by using Zero-Delay Mode (ZDM), either Cascaded or Nested, but it isn’t obvious if hitless switching is available in ZDM.  I am also unsure if the cascaded ZDM configuration is deterministic to the input clock or to just the PLL1 VCXO.

    Thanks!

  • +1 in reply to Cameron Wutzke
    TI__Genius 10995 points

    Hello Cameron,

    I tested the LMK04828 set up in both ZDM modes and hitless switching continued working. Just make sure to enable holdover and hitless switch (HOLDOVER_EN = 1 and HOLDOVER_HITLESS_SWITCH = 1).

    Cameron Wutzke said:
    I am also unsure if the cascaded ZDM configuration is deterministic to the input clock or to just the PLL1 VCXO.

    It is deterministic to the PLL2 input clock (OSCin), which is the same as the output of the VCXO, and the output clock (p. 33 of data sheet).

    Hope this helps.

    Best,

    Andrea