CDCLVC1310: input slew rate requirement

Chi Zhang2

Part Number: CDCLVC1310

Hi Expert,

my customer is using CDCLVC1310 in server mother board, as single-end LVCMOS 50MHz input and output for FPGA system reference clock, but we don't find the input slew rate in datasheet, could you help to check it? thanks.

Chi

over 3 years ago

0 Asim Khan over 3 years ago

TI__Genius 9260 points

Hi Chi,

A similar device has a slew rate requirement of 2 V/ns for good performance. I would suggest the same for this device for best AC performance. Device would be functional as low as 0.5 V/ns.

Best,

Asim

Clock & timing

Clock & timing forum

CDCLVC1310: input slew rate requirement