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LMX2820: Output phases relationship on the RFOUTA/RFOUTB

Matteo Ricci
Prodigy 230 points
Part Number: LMX2820

Hi Team,

We are working with the LMX2820 as sample clock generator for 2 chips ADCs, using the configuration for the LMX indicated in the .tcs attached. 

We approaching the syncronization between the 2 ADCs, however we have some doubts about the sample clocks generated by the LMX.

  1. The channel divider is unique for both outputs or each have a dedicated divider? In the SNAS783C, in the block diagram of section 7.2 is indicated a divider for each channel, however in the section 7.3.8 Fig 7.1 is indicated a single divider for both output channels. Which one is correct?
  2. Using those dividers, there can be an 180° offset between RFOUTA & RFOUTB channels of the same LMX?
  3. The working mode in fractional of the PLL, how affects the output channels? There can be a non deterministic phase of the outputs?
  4. The Cat.3 of the UG SNAU273, is valid also for the single PLL? If yes, is necessary an external PSYNC also for the single PLL in order to obtain the phase determinism on the output clocks?

Thank you all,

Best regards!

PLL1_OUTA_OUTB_new.tcs

  • 0
    TI__Guru** 108130 points

    Hi Matteo,

    Section 7.3.8 is the details on the channel divider while the block diagram is a simplified version. Both output share the same divider, the signals going to the outputs could be tapped out in the middle of the divider, that's why we can virtually support independent division.

    Correct, whenever divider is used, both output phases may not be identical after every power cycling or programming.

    Fractional channels will usually put it in Cat. 3 or Cat. 4 sync, that means the phases are not deterministic. 

    Phase synchronization of the LMX2820 means that the delay from the rising edge of the reference clock signal to the output signal is deterministic. Input clock is the reference, not the output frequency of other devices.

  • 0
    Prodigy 230 points

    Hi Noel,

    Thank you for your reply. 

    Noel Fung said:

    Correct, whenever divider is used, both output phases may not be identical after every power cycling or programming.

    When you refer to that, may be that the output phases of the same PLL has an offset of 180°?

    In order to guarantee the phase relationship deterministic on the same PLL, is necessary the use of PSYNC or is possible to "calibrate" the device in other way?

    Thank you very much,

    Best regards!  

  • 0 in reply to Matteo Ricci
    TI__Guru** 108130 points

    Hi Matteo,

    A div-by-2 will return two possible phases, 0° or 180°. Higher division ratio will return more possibility. Below application note has the details.

    https://www.ti.com/lit/pdf/SNAA060

    Please read the user's guide, SNAU273, again, it tells you how to sync.