CDCEL913-Q1: cdcel913 driver

Hi Huizhou,

What driver you are referring to?

Can below application note help you?

https://www.ti.com/lit/pdf/scaa105

My input frequency is 27 mhz, and I want to output 184 mhz. But I don't know how to configure registers.The register values I read are 0x07 or 0x01.

N and M are shown in the figure,N=3312，M=486.The calculated R value is not within the specified range。

This is my register configuration. However, I obtained that the output frequency is not stable, approximately 178mhz. Can you help me check whether the register configuration is correct.

Hi Huizhou,

What is 941?

Could you clarify what is "screen blur phenomenon"?

Ds90ub941as q1 is a deserializer. I use 913 as the reference clock for 941 here. I only need to configure the value of the 0x56 register as 0x01. Do I need to configure any other registers.I am using the splitter mode. When 913 outputs 184mhz to 941, one screen has vertical stripes and the other screen is black.

HI Noel Fung,

I have encountered a new problem.My input frequency is 27 mhz.I want Y1 to output 192mhz and Y2 to output 184mhz.

1.This is my configuration.I have configured two outputs.

2.But the result I got was two Y1 outputs.What is the function of this select button.

   How can I configure to obtain two outputs Y1 and Y2 at once.

Thank you for your support

Regards,

Huizhou

HI Noel Fung,

The following figure shows the output I obtained after using cdce925.

But we have already used the machine of cdcel913 and it is already in production.

Do we have to switch to cdce925 in this case? Does it mean that cdcel913 cannot meet our requirements for both Y1 and Y2 outputs?

Thank you for your support

Regards,

Huizhou

HI Noel Fung,

When I use the 192mhz clock frequency divided by 8155, the screen can display stably.

When using the 192mhz clock frequency given by cdcel913, it was found that there was a slight jitter in the frequency and a jagged pattern around the image.

From the oscilloscope, it can be seen that the frequency of the REFCLK pin of 941 is also unstable.

Thank you for your support

Regards,

Huizhou

I used the 941 splitter mode, do I need to configure the 941 register when using the 913 clock frequency. Now only the 0x56 register of 941 is configured.

Hi Noel，

I am the FAE who supports Pateo, we don’t have to worry about the related settings of FPDLINK, and now I want to help customers confirm whether CDCEL913 can be configured with Y1 to output 192mhz and Y2 to output 184mhz.

Noel Fung said:

913 cannot generate two non-integer multiple clock frequencies simultaneously. 

Is the integer multiple mentioned here 10 as an integer? Such as 180, 190, etc. Or the ones digit is an integer, and there is no decimal point.

Can I only switch to CDCE925 for the above requirements?

Thanks！

Hi Noel,
After I studied it, I understood that the integer multiple refers to the multiplier input frequency. May I ask if there is a way to use 913 to output 184M and 192M？

Hi Noel,

Yes, I  got it.

I tried to use Clock Pro to make two clocks, but I still couldn't make them. It seems that it can only be replaced by CDCEL 925.