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Original question:

LMK03318: Default settings in EEPROM at soft pin mode

LMK03318: When hardware register default settings in Soft pin mode, does the clock output nothing or something?

Hiroyuki IRIKURA
Prodigy 40 points
Part Number: LMK03318


Hello. I have a question.

 

We used under the following conditions:

HW_SW_CTRL = 0 (=Soft pin mode)

REFSEL = 1

(GPIO5, GPIO4, GPIO3, GPIO2, GPIO1, GPIO0) = (0, 1, Floating, Floating, 1, 1)

 

Chap.10.3.2.2 notes that when GPIO[3:2] are left floating, the hardware register default settings are loaded.

https://www.ti.com/document-viewer/ja-jp/LMK03318/datasheet/57-JAJSFA5E#SNAS6696874

In this case, when PRIREF is a single-ended clock and SECREF is GND, will the clock of OUT0_P and OUT0_N be something output?

Could you tell me if there is no or some clock output until clock output mutes before starting re-programming the desired register reprogramming via I2C?

  • 0
    TI__Mastermind 22760 points

    Hello,

    One of our experts will reach out with a response within 24 hours of this message.

    Thanks,

    Kadeem

  • 0
    TI__Mastermind 18950 points

    Hi Hiroyuki,

    I looked at the default register settings for this device and I would expect active clock outputs when they are loaded in the situation you described. I found some discrepancies in the datasheet and am not sure exactly what those active clock outputs would be. I will check with my team tomorrow, if there is anything else important that you should know I will post another update.

    Thanks,

    Evan Su

  • 0 in reply to Evan Su
    Prodigy 40 points

    Hello, Kadeem, Evan Su,

     

    Thank you for your help.

    Let me know if you find anything new.

    Thanks.

  • 0 in reply to Hiroyuki IRIKURA
    Prodigy 40 points

    Hello.

     

    I tried.

    First,

    A single-ended clock inputs to PREREF pin.

     

    Second,

    I operate PDN pin Low to High and write nothing via I2C.

    Then, OUT0_P and OUT0_N are nothing output.

     

    Next,

    With the exception of the read-only register, I write in order from R0 to biggest register number.

    I confirmed the clock is output immediately after writing R57.

    Is the above working of IC correct?

     

    After all, when being the default register setting, are OUT0_P and OUT0_N no output?

     

    I know I need to check PLL Lock via STATUS0 pin because the output clock would be unstable for a litter while after programming.

     

    Thank you.

  • 0 in reply to Hiroyuki IRIKURA
    TI__Mastermind 22760 points

    Hiroyuki-san,

    Neither the PLL nor the output are disabled with these default settings, so if a valid input clock is supplied, there can be an output clock - loading the register default settings into TICS Pro will allow you to better visualize these settings.

    Your procedure is correct - once a valid configuration is written, an output clock is expected.

    Thanks,

    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 40 points

    Hello, Kadeem-san

    We still do not sign your SLA(Software Licence Agreement) to use TICS Pro because our legal office need long long long time to check.

    The R12.2 default register setting is 0. You recommend R12.2 set to 1. When I still let IC be default setting, do you mean IC output something?

    I don't really know the difference between "Always On Clock" and "VCO Clock" because the datasheet of R12.2 say nothing about.

    Thanks.

  • 0 in reply to Hiroyuki IRIKURA
    TI__Mastermind 22760 points

    Hiroyuki,

    What are you referring to with "You recommend R12.2 set to 1"?
    Thanks,

    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 40 points

    Hello Kadeem-san,

    Please see below page. It's a part of the datasheet.

    LMK03318 datasheet chap.10.6.10 DEV_CTL Register; R12

    The description of AONAFTERLOCK(R12.2) says that TI recommends setting the AONAFTERLOCK to 1.
    So, do you mean you recommend R12.2 set to 1?

    Thanks.

  • 0 in reply to Hiroyuki IRIKURA
    TI__Mastermind 22760 points

    Hiroyuki-san,

    My apologies, I misread your question. There is an additional internal clock, the "always-on clock", that can be used for the system as opposed to the VCO clock. if there is an issue with the VCO clock (i.e. if the PLL is not locked), then SRAM reads, SRAM writes, etc. will not be available. Switching to the always-on clock prevents this issue. This is why we recommend setting the bit to '1' - if the PLL is not locked, these features are still accessible.

    Thanks,

    Kadeem

  • +1 in reply to Kadeem Samuel
    Prodigy 40 points

    Hello Kadeem-san,

    Sorry for long time no reply.
    I see, that's why you recommend setting it to 1. I understood very well.

    By default settings, always-on clock is set to OFF, LMK03318 can receive a differential signal.
    If the input signal is a single-end signal, you don't know the IC outputs anything.

    At first, I expected the IC output nothing by default.
    But, there is a possibility of some kind of output, I got it.

    During periods when write registor via I2C, I should the back end circuit mutes IC's output signal.

    Thanks.