LMK04821: PLL2 cannot be locked in single-loop mode

Cherry Zhou

Part Number: LMK04821

Hi team,

Here's an issue from the customer may need your help:

Using the single PLL mode of the LMK04821, input a differential clock of 125 MHz from the OSCin and please see the configuration parameters: https://e2echina.ti.com/cfs-file/__key/communityserver-discussions-components-files/124/lmk04821_5F00_single_5F00_pll_5F00_OSCin_5F00_VCO0.tcs

During the test it was found that the output clock frequency was basically correct, but PLL2 could not be locked.

The customer would like to know what could be the possible cause and how to fix it? Could you please help look into this case? Thanks.

Best Regards,

Cherry

over 2 years ago

0 Noel Fung over 2 years ago

TI__Guru** 108270 points

Hi Cherry,

If the output frequency is correct, phase noise is normal, then it should have locked. When you said PLL2 could not lock, did you mean the PLL2 DLD is low?

Please use spectrum analyzer or other RF test equipment to measure PLL2 output to confirm it is locked.

How did you connect the differential clock to OSCin?

0 Cherry Zhou over 2 years ago in reply to Noel Fung

TI__Mastermind 22235 points

Hi Noel,

Thanks for your support.

1) Through the Status_LD2 hardware pins and the 0x183 register, it can be seen PLL2 DLD is both low.

2) And the customer also reviewed the outdated clock spectrum and find that the center frequency is drifting.

Based on the above two points, it can be determined that the PLL does not lock.

And please see the LMK04821 hardware schematic:

https://e2echina.ti.com/cfs-file/__key/communityserver-discussions-components-files/124/LMK04821.pdf

Thanks and Regards,

Cherry

0 Noel Fung over 2 years ago in reply to Cherry Zhou

TI__Guru** 108270 points

Hi Cherry,

Clock & timing

Clock & timing forum

LMK04821: PLL2 cannot be locked in single-loop mode