Other Parts Discussed in Thread: CLOCK-TREE-ARCHITECT, , LMK04828
Hello,
My customer would like to have a PLL solution for the following requirements.
Input = 155.52MHz
Output#1 = 2488.32MHz
Output#2 = 1244.16MHz
Output#3 = 311.04MHz
Output#4 = 19.44MHz
With this requirements, TI “clock-tree-architect” shows only two device solutions.
However, using only the 2nd PLL of LMK04228 (155.52MHz -> OSCin), I think one LMK04822 can support all the four output frequency above as attached .tcs file. Is my understanding correct?
LMK04228.tcs
Best regards,
K.Hirano
