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LMK04832: Clock and SYSREF Output Polarity

IDK
Prodigy 230 points
Part Number: LMK04832

Hi,

The TICS Pro register description of the DCLKX_Y_POL indicates that this register has "no effect in bypass mode", but the register description in the datasheet indicates that the register "also applies to CLKoutX in high performance bypass mode". Which is correct?

Overall, I would like to have the ability to invert the polarity of specific differential clock outputs and specific differential SYSREF outputs. Are there any situations in which this is not possible or allowed?

Thanks,

Matthew

  • 0
    TI__Guru** 107030 points

    Hi Matthew,

    If we "bypass" the divider, we will bypass the inverter as well, as a result, we cannot invert the output clock polarity. The output format is also restricted to CML.

    We can keep the divider active but set it to div/1, in this case, DCC&HS bit must be =1, we can use the Polarity bit to invert the output clock signal.

    SYSREF has its own inverter, the above restrictions do not apply.