CDCLVP1204: Buffer output rise and fall time related questions consultation

Hi Asim，

I understand that what you said means that the Input edge rate parameter of CDCV1204 should be satisfied, right？

As for the device CDCV304, there is no Input edge rate requirement in the specification. Can this device ignore the influence of input? If so, why is there such a difference, can you explain it in more detail in terms of architecture, thank you very much

Hi Qujindong,

For CDCV304, you are right. There is no input slew rate specification but looking at the output slew rate specification of the same device, we can say that it needs 1.5 V/ns for good working if you consider cascading these two buffer together. This is just an assumption, I am not sure about the actual specification since this is an old part. 

qujindong said:

can you explain it in more detail in terms of architecture

They are both different buffer types, differential and LVCMOS. I will get more detail about major differences and get back to you.

Best,

Asim

Hi Asim，

Thank you for your reply!

For the initial question has been answered, for CDCV1204 needs to meet the requirements of the input clock slope in order to achieve the specification output.

I also noticed that for LMK00301, there is no requirement for input slope in the specification. This should be strongly related to design. If your company has published relevant learning materials, I hope you can send them to me for my study. Thank you very much!

Hi Asim，

If CDCV304 is used alone and I use crystal input at the front end, should the output slope of CDCV304 not be affected by the input?

Hi Quindong,

CDCV304 should be okay with crystal input. Let me elaborate further what we meant with the slow input signal. When you have extremely slow input transition and if the part doesn't have any hysteresis, it could result in chatter on the output which shows up as glitches on the outputs. We have not experimented this to see if this results in degraded rise and fall time on the output of the buffer. But this could cause problems for outputs due to chatter or glitches.

Input slew rate is a number that we simulate and test for each device and it could vary by each device family. 

Best,

Asim

Hi Asim，

Because I do not know the internal design of the chip, my guess is that the crystal oscillator such as CDCV304, which does not give the slope requirement of the input signal, under normal working environment, when the input signal level is higher than VIH, the output signal will be high level. When the input signal level is lower than VIL, the output signal is low. Therefore, when the slope of the input signal is monotonous, the speed of the input slope only affects the duty ratio of the output signal.

May I understand it in this way？