LMK04832: no outputs

If you're using TICS Pro, can  you save the configuration as either tcs or hex file and upload for review? There's a lot of things that could be wrong, and without the register state it's difficult to narrow them down.

Hi,

Please see attached register settings from TICS Pro. Thank you very much for the quick response. 

R0 (INIT) 0x000090
R0 0x000010
R2 0x000200
R3 0x000306
R4 0x0004D1
R5 0x000563
R6 0x000650
R12 0x000C51
R13 0x000D04
R256 0x01001E
R257 0x01010A
R258 0x010200
R259 0x010340
R260 0x010410
R261 0x010500
R262 0x010601
R263 0x010755
R264 0x01081E
R265 0x01090A
R266 0x010A00
R267 0x010B40
R268 0x010C10
R269 0x010D00
R270 0x010E01
R271 0x010F65
R272 0x01101E
R273 0x01110A
R274 0x011200
R275 0x011340
R276 0x011410
R277 0x011500
R278 0x011601
R279 0x011765
R280 0x01181E
R281 0x01190A
R282 0x011A00
R283 0x011B40
R284 0x011C10
R285 0x011D00
R286 0x011E01
R287 0x011F33
R288 0x012008
R289 0x01210A
R290 0x012280
R291 0x012340
R292 0x012410
R293 0x012500
R294 0x012601
R295 0x012700
R296 0x012808
R297 0x01290A
R298 0x012A80
R299 0x012B40
R300 0x012C10
R301 0x012D00
R302 0x012E01
R303 0x012F00
R304 0x01300C
R305 0x01310A
R306 0x013200
R307 0x013340
R308 0x013410
R309 0x013500
R310 0x013601
R311 0x013733
R312 0x013825
R313 0x013900
R314 0x013A0C
R315 0x013B00
R316 0x013C00
R317 0x013D08
R318 0x013E03
R319 0x013F80
R320 0x014007
R321 0x014100
R322 0x014200
R323 0x014311
R324 0x014400
R325 0x014500
R326 0x014618
R327 0x01471A
R328 0x014802
R329 0x014942
R330 0x014A03
R331 0x014B06
R332 0x014C00
R333 0x014D00
R334 0x014EC0
R335 0x014F7F
R336 0x015001
R337 0x015102
R338 0x015200
R339 0x015300
R340 0x015478
R341 0x015500
R342 0x015678
R343 0x015700
R344 0x015896
R345 0x015900
R346 0x015A78
R347 0x015BD4
R348 0x015C20
R349 0x015D00
R350 0x015E1E
R351 0x015F0B
R352 0x016000
R353 0x016101
R354 0x01624C
R355 0x016300
R356 0x016400
R357 0x01650C
R361 0x016958
R362 0x016A20
R363 0x016B00
R364 0x016C00
R365 0x016D00
R366 0x016E13
R371 0x017310
R375 0x017700
R386 0x018200
R387 0x018300
R358 0x016600
R359 0x016700
R360 0x01680F
R1365 0x055500

Thanks for the registers. I see a potential source of the problem: you have all the SYNC disable bits (SYNC_DISx) cleared, and the SYNC path allows signals from both CLKin0 and the SYNC pin. If the SYNC pin is high, or if the CLKIN0 path is in some way getting noise-triggered high, these signals will hold the output dividers in reset and you will not see an output signal. You can try setting the SYNC_DISx bits (write 0x0144FF or in TICS Pro go to SYNC/SYSREF page and toggle "all on" in the yellow box on the right) and see if this ungates outputs.

Let me know if you still have problems after modifying these settings.

---

There's a few other things I saw which aren't related to the outputs not showing, but which could be addressed at some point:

• Set PLL2_N_CAL equal to PLL2_N to ensure proper calibration of PLL2 across temperature
• Set PLL1_PD and OSCin_PD since these functions are not used
• Set OSCout_FMT to Powerdown since this function is not used

Hi, 

I changed register 0x0144 to xFF. Still no outputs and PLL2 is not locked neither. 

Okay. Can you check if there is any register communication at all? For instance, can you set the POWERDOWN bit (on the User Controls page, first group), and observe if the supply current to the system is changing? If this is not feasible in your setup, can you read back the values of registers 3/4/5/6 and check that the device is communicating?

I kind of got clock outputs by connecting OSCin with a 100MHz . It seems that it does not take CLKin1? 

Hi Derek,

There is a default setting from TICS Pro. 

Could you confirm this default settings?

Was it power-on default? 

Was it single-loop PLL2 with CLKin1 to PLL2? Thank you.

POR default should hold outputs in powerdown, except OSCout which will either reflect the signal on OSCin or self-oscillate at ~500MHz with no input applied. Neither PLL should be locked at POR. So if you're not sending register communication, you could likely see OSCout at the same frequency as OSCin, but the clock outputs should still be held in powerdown.

The VCO_MUX defaults to CLKin1 as signal source, so any leakage through the outputs in powerdown state should theoretically be a divide of the CLKin1 signal (as though in distribution mode). PLL1 and PLL2 are both powered down at startup.

The default configurations in TICS Pro are not actually POR defaults unless it explicitly says so; instead, they are the default configuration that works with the EVM, or that demonstrates some behavior in an application note or reference design. The default configuration provided by TICS Pro for the LMK04832 profile configures the device as described in the LMK04832EVM user's guide - PLL1 and PLL2 on, all input frequencies and output formats configured according to formats that match EVM defaults.