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LMK1C1104: Clock Architecture for DP83869HM Ethernet PHY

Harikrishnan Thangamani
Prodigy 60 points
Part Number: LMK1C1104
Other Parts Discussed in Thread: DP83869HM, , LMK1C1108

Hi Everyone,

Clocking Architecture for DP83869HM Ethernet PHY:

In my design I have 14 Ethernet Interfaces. 10 was configured as 1000BASE-T and 4 was 100BASE-TX.

For that I am sharing common clock with buffers.

Using MEMS Oscillator SiT8924BA in my design as source and LMK1C1104 as Buffer to share the clock to multiple Ethernet PHYs.

Still my architecture on clock was open, I have two ideas in my mind.

1. Individual Oscillators for Individual PHYs

2. Single Oscillator with multiple clock buffers

Which is the best idea as per your thoughts ? If you have any other ideas please let me know.

For both ideas what is the layout and routing recommendations on clock signals to anticipate EMI Issues.

Please resolve my queries at the earliest.

Regards,

Harikrishnan T

  • 0
    TI__Prodigy 720 points

    Hi Harikrishnan,

    Based on my understanding of your situation, I would recommend option 2.

    I'm having trouble visualizing what you mean by your clock architecture still being open, can you clarify in what way? If you have a clock architecture with each signal routed to a PHY, I don't see how it would be open. Or are you saying you are open to which way you design your clock architecture?

    Regarding the layout and routing recommendations, I've pinged a colleague of mine that will be able to further assist. He will return to the office on Monday.

    Regards,

    Juan

  • 0 in reply to Juan Rodriguez
    Prodigy 60 points

    Hi Juan,

    To clarify your doubt, I am open to the idea in designing the clock architecture.

    Regards,

    Harikrishnan T

  • 0 in reply to Harikrishnan Thangamani
    TI__Genius 11900 points

    Hi Harikrishnan,

    Typically we recommend that you use clock buffers to fan out the signal from a small number of oscillators, because this is easier to manage than having lots of oscillators. You may consider using more oscillators and smaller buffers if there is not enough board space to route many clock lines through a large buffer, or if you want to reduce the overall disruption if one of the oscillators were to misbehave or fail for some reason, but these considerations are very dependent on the customer and system so it is hard to say much from here.

    Harikrishnan Thangamani said:
    For both ideas what is the layout and routing recommendations on clock signals to anticipate EMI Issues.

    In a clock buffer the output lines are not likely to cause significant crosstalk with each other because they should be running at the same frequency, so it should be enough to provide reasonable spacing between outputs. For reducing EMI radiated out of the system, the only specific methods I am aware of are providing shielding around the active clocks/clock lines and avoiding the creation of accidental antennas on the PCB layout (although I was taught this in the context of switching power supplies, for clock signals it should not be a common error).

    Our clock buffer expert will reply when he is available.

    Best,

    Evan Su

  • 0 in reply to Evan Su
    Prodigy 60 points

    Hi Evan,

    I have one question on trailing reply, I want to know more on why you prefer clock buffer idea ?

    What is the reason behind that ? Can you give explanation on that /

    Regards,

    Harikrishnan T

  • 0 in reply to Harikrishnan Thangamani
    TI__Genius 9250 points

    Hi Harikrishnan,

    Oscillator + clock buffer is cheap in terms of cost because you would have one oscillator and it we can fan out with a LMK1C1108 and LMK1C1104 buffer. But if clock needs to go to components which are separated or on a different board then it becomes cumbersome to control skew between different channels. This applies if skew is an important consideration which I don't think would matter for your reference clock requirements. You can check that in your design requirements.

    You can also have small sub system where you have multiple oscillator + buffer combination or oscillator source but now you have more jitter sources in your system and more component but this is helpful to reduce trace length compared to other one. (Jitter assumption is true when you have TX and RX and they use different clock sources.)

    It would be also helpful if you could share a block diagram of clock tree to understand your clock requirements and how we can handle that. 

    This reference clock is 25 MHz which is same across all channels, so if we follow layout guidelines for high speed clock routing then there shouldn't be any EMI issue.

    For lower jitter performance, you can also look at LMK6X BAW oscillator for your needs. It has low jitter which could help if you want to add multiple oscillator. 

    Best,

    Asim