Other Parts Discussed in Thread: DP83869HM, , LMK1C1108
Clocking Architecture for DP83869HM Ethernet PHY:
In my design I have 14 Ethernet Interfaces. 10 was configured as 1000BASE-T and 4 was 100BASE-TX.
For that I am sharing common clock with buffers.
Using MEMS Oscillator SiT8924BA in my design as source and LMK1C1104 as Buffer to share the clock to multiple Ethernet PHYs.
Still my architecture on clock was open, I have two ideas in my mind.
1. Individual Oscillators for Individual PHYs
2. Single Oscillator with multiple clock buffers
Which is the best idea as per your thoughts ? If you have any other ideas please let me know.
For both ideas what is the layout and routing recommendations on clock signals to anticipate EMI Issues.
Please resolve my queries at the earliest.