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LMK03328: Output freq synchronization

Austin Do
Expert 4155 points

Part Number: LMK03328

Hello team,

My customer is using LMK03328, but there is an issue when they changed output freq value.

If they changed the frequency at output 6 & 7, both output does not synchronize

Can you please let us know which register setting can resolve this?

Best Regards,

Austin

  • 0
    TI__Mastermind 18780 points

    Hi Austin,

    It should be possible to resynchronize the outputs by manually triggering the output synchronization feature through either a GPIO pin or through register 12.6, see section 10.4.17 of the LMK03328 datasheet.

    Best,

    Evan Su

  • 0 in reply to Evan Su
    TI__Expert 4155 points

    Hi Evan,

    Thanks for reply.

    It seems minimum SYNCN width is required as datasheet. If the customer violate this, what happens?

    I'm not fully understanding Figure 69. 

    The rising edge of SYNCN should be in one clock cycle before 4th edge of ref clock. Is this right?

    Best Regards,

    Austin

  • 0 in reply to Austin Do
    TI__Mastermind 18780 points

    Hi Austin,

    If the minimum SYNCN time is not met, some of the output dividers may not be reset properly and the synchronization would not be successful. I don't quite understand Figure 69 either, so I will check with my team and let you know.

    Best,

    Evan Su

  • 0 in reply to Evan Su
    TI__Mastermind 18780 points

    Hi Austin,

    I am told that Figure 69 is saying that if the rising edge of SYNCN happens at a window around the current PLL clock cycle (in this example it is clock cycle #3), the process of restarting the output buffers will initiate on the next rising edge (in this example that is the rising edge for clock cycle #4). I think you can hold SYNCN as long as you want, does not absolutely need to be 1 clock cycle before 4th edge of ref clock.

    Best,

    Evan Su