LMK04832: SYSREF outputs

new2day

Expert 1940 points

Part Number: LMK04832

We are trying use this device as single loop PLL2 mode and distribution mode with CLKin1 as REF IN.

Only use CLKout0/1, CLKout2/3, CLKout4/5 and CLKout6/7 for now.

1. single PLL2 mode with CLKin1

PLL2 is locked and DEVICE CLK outputs are fine. However there are no SYSREF outputs (see attached register dump)

2. distribution mode with CLKin1

Both clock and sysref output frequencies are fine, 100MHz and 0.1953125MHz (sysref) when CLKin1 is 400MHz

However the frequencies are not right when CLKin1 is 100MHz.

Here are the interesting things,

1) both clock and sysref frequency are divided by 4 if just changing the CLKin1 Freq and other settings are stay so that it seems OK

2) If the clock output Freq is set to 100MHz (the same as CLKin1, the actual Freq measured is 33.333MHz.

Fullscreen default_to_single_clkin1_pll2_100m_2m5_vco0_2500m_pll1LD_to_pll2LD_CLKin0_to_CLKin1.txt Download

R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R3	0x000306
R4	0x0004D1
R5	0x000563
R6	0x000650
R12	0x000C51
R13	0x000D04
R256	0x010019
R257	0x01010A
R258	0x010200
R259	0x010340
R260	0x010410
R261	0x010500
R262	0x010601
R263	0x010755
R264	0x010819
R265	0x01090A
R266	0x010A00
R267	0x010B40
R268	0x010C20
R269	0x010D00
R270	0x010E01
R271	0x010F65
R272	0x011019
R273	0x01110A
R274	0x011200
R275	0x011340
R276	0x011420
R277	0x011500
R278	0x011601
R279	0x011765
R280	0x011819
R281	0x01190A
R282	0x011A00
R283	0x011B40
R284	0x011C20
R285	0x011D00
R286	0x011E01
R287	0x011F65
R288	0x012008
R289	0x01210A
R290	0x012200
R291	0x012340
R292	0x012420
R293	0x012500
R294	0x012601
R295	0x012760
R296	0x012808
R297	0x01290A
R298	0x012A80
R299	0x012B40
R300	0x012C10
R301	0x012D00
R302	0x012E01
R303	0x012F00
R304	0x01301A
R305	0x01310A
R306	0x013280
R307	0x013340
R308	0x013410
R309	0x013500
R310	0x013601
R311	0x013733
R312	0x013805
R313	0x013900
R314	0x013A03
R315	0x013BE8
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013F80
R320	0x014091
R321	0x014100
R322	0x014200
R323	0x014311
R324	0x0144FF
R325	0x014500
R326	0x014610
R327	0x01471B
R328	0x014802
R329	0x014942
R330	0x014A03
R331	0x014B06
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015001
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015678
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A78
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E1E
R351	0x015F13
R352	0x016000
R353	0x016101
R354	0x0162AC
R355	0x016300
R356	0x016400
R357	0x016505
R361	0x016958
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017310
R375	0x017700
R386	0x018200
R387	0x018300
R358	0x016600
R359	0x016700
R360	0x016805
R1365	0x055500

Regaiter dump for distribution with CLKin1

Fullscreen pll2222b_0525_100m_1m25_0504.txt Download

R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R3	0x000306
R4	0x0004D1
R5	0x000563
R6	0x000650
R12	0x000C51
R13	0x000D04
R256	0x010001
R257	0x01010A
R258	0x010200
R259	0x010340
R260	0x010410
R261	0x010500
R262	0x010601
R263	0x010755
R264	0x010801
R265	0x01090A
R266	0x010A00
R267	0x010B40
R268	0x010C20
R269	0x010D00
R270	0x010E01
R271	0x010F65
R272	0x011001
R273	0x01110A
R274	0x011200
R275	0x011340
R276	0x011420
R277	0x011500
R278	0x011601
R279	0x011765
R280	0x011801
R281	0x01190A
R282	0x011A00
R283	0x011B40
R284	0x011C20
R285	0x011D00
R286	0x011E01
R287	0x011F15
R288	0x012001
R289	0x01210A
R290	0x012200
R291	0x012340
R292	0x012400
R293	0x012500
R294	0x012601
R295	0x012711
R296	0x012801
R297	0x01290A
R298	0x012A80
R299	0x012B40
R300	0x012C10
R301	0x012D00
R302	0x012E01
R303	0x012F11
R304	0x013001
R305	0x01310A
R306	0x013280
R307	0x013340
R308	0x013410
R309	0x013500
R310	0x013601
R311	0x013711
R312	0x013845
R313	0x013903
R314	0x013A00
R315	0x013B50
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013F00
R320	0x0140F1
R321	0x014100
R322	0x014200
R323	0x014311
R324	0x0144FF
R325	0x014500
R326	0x014610
R327	0x014702
R328	0x014802
R329	0x014942
R330	0x014A03
R331	0x014B06
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015001
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015678
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A78
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E1E
R351	0x015F0B
R352	0x016000
R353	0x016101
R354	0x01624C
R355	0x016300
R356	0x016400
R357	0x01650C
R361	0x016958
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017370
R375	0x017700
R386	0x018200
R387	0x018300
R358	0x016600
R359	0x016700
R360	0x01680C
R1365	0x055500

over 2 years ago

0 new2day over 2 years ago

Expert 1940 points

I may know why. The SYSREF_MUX needs to be set to SYSREF_Continuous. Is it right?

Still need support for the distribution mode (item2 above) thank oyu.

0 Evan Su over 2 years ago in reply to new2day

TI__Mastermind 18575 points

Hi new2day,

In the first case the SYSREF is configured as Normal SYNC, so the SYSREF outputs will not do anything unless manually triggered. For a continuous clock output it should be SYSREF_Continuous as you said.

We will look into the second case. Do you have a TICS Pro configuration file (.tcs) for it so we can get a better picture of the clock inputs? When I loaded the registers it looked like CLKin0 was being manually selected as a reference input even though it was not enabled.

Best,

Evan Su

0 new2day over 2 years ago in reply to Evan Su

Expert 1940 points

For item2, CLKin1 has been used in both 400MHz and 100MHz input. Thank you.

pll2222b_0525_100m_1m25_0504.tcs

0 Evan Su over 2 years ago in reply to new2day

TI__Mastermind 18575 points

Hi new2day,

Thanks for the configuration, we will look at it next week.

Best,

Evan Su

0 Ajeet Pal over 2 years ago in reply to Evan Su

TI__Genius 12560 points

Hi new2day,

The configuration file for the distribution mode, seems to be used the same clock output frequency as CLKin1 input. Hence, you need to be enable the Bypass Div bit for individual clock out channels. 0x103[3] should be high for CLKout0 bypass clock. If wants to use the divider frequency, disable the 0x103[3] -->0 and change the DCLK0_1_DIV value for desired divided frequency.

Thanks!

Regards,
Ajeet Pal

edited: R0x103[4] changed to 0x103[3].

0 new2day over 2 years ago in reply to Ajeet Pal

Expert 1940 points

Hi Ajeet,

There are no clock outputs at all after set Bypass Div. Thanks.

0 Ajeet Pal over 2 years ago in reply to new2day

TI__Genius 12560 points

Hi new2day,

Sorry for the correction on the above response typo error.

For the DCLK0_1_BYP, the bit would be 0x103[3] instead of [4]. I believe, you have tried the Bypass DIV with 0x103[3] --> 1 only. Please confirm?

For clock divider value 1, enable the duty cycle correction bit 0x103[2] -->1.

Thanks!

Regards,

Ajeet Pal

0 new2day over 2 years ago in reply to Ajeet Pal

Expert 1940 points

Hi Ajeet,

Yes. 0x103[3] = '1'. so the value is from 0x"40" to x"48", see attached .tcs file, in which CLKout0 is set to bypass Divider.

CLKout0 has no outputs afterwards while CLKout1 is still 33.3MHz. Thank you.

pll2222b_0525_100m_1m25_0504_disDIV_CLKout0.tcs

0 new2day over 2 years ago in reply to Ajeet Pal

Expert 1940 points

any updates? Thank you.

Here is the problem to have 100MHz outputs with CLKin1 = 100MHz

1. it's 33.3MHz if 0x103[3] = 0 and divider value 1

2. no output if 0x103[3] = 1

0 Evan Su over 2 years ago in reply to new2day

TI__Mastermind 18575 points

Hi new2day,

I will check with Ajeet.

Best,

Evan Su

+1 Ajeet Pal over 2 years ago in reply to Evan Su

TI__Genius 12560 points

Hi new2day,

You can ignore the bypass bit, which supports the CML output at high frequency output.

As mentioned in previous reply, for clock divide 1, you need to enable the duty cycle correction bit 0x103[2] -->1, which update the correct frequency and duty cycle.

Thanks!

Regards,

Ajeet Pal

0 new2day over 2 years ago in reply to Ajeet Pal

Expert 1940 points

Hi Ajeet,

I got 100MHz from CLKout0 and CLKout1 after set register 0x103 bit[2] to '1'. Thank you.

Clock & timing

Clock & timing forum

LMK04832: SYSREF outputs