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LMK03328: I2C timing requirement

Part Number: LMK03328


Hello,

Please refer the attached waveforms.

At normal timing transaction, ACK is returned.  

However if we put around 3sec waiting time before sending slave address, No ACK is happened.

 

It seems LMK03328 I2C interface has maximum timing requirement before sending slave address.

But we can't find this specification on the datasheet.

What is maximum timing specification of slave address transaction after the start condition?

I2C standerd specification said it is minimum 4.7usec but there is not maximum limitation. 

Regards,

Mochizuki

  • Mochizuki-san,

    Where is the 9th clock pulse in the second capture? I only see the first eight, followed by a rising edge that does not go back down on CLK. Does the ACK occur if the 9th pulse is present?

    Thanks,

    Kadeem

  • Hi Samuel,

    Thank you for your prompt reply.

    There is 9th rising edge but SDA is still High, even if we input complete 9th pulse ACK will not be returned.   

     

    In other words, tw(SCLL) is appeared on Figure71  I2C timing diagram.

    This specification is exactly what we want to know in this use case.

    What is the acceptable range of Tw(scll) on LMK03328? It doesn't show up on the datasheet.

     

    Regards,

    Mochizuki

  • Mochizuki-san,

    I would advise keeping the hold time between sending the start condition and writing address/data capped at the maximum SDA Hold Time, 0.9 us.

    Is there any reason why the start condition must be sent several seconds beforehand?
    Thanks,

    Kadeem

  • Hi Kadeem,

    In the market some of I2C devices have timeout condition if there is long enough waiting time after start condition.

    That is why we had tried to see the behavior of LMK03328 I2C engine. Resulted in when we applied 3sec waiting time no ACK is returned but with 100msec waiting time ACK is returned.

     

    On the datasheet section 8.23 I2C-Compatible Interface Characteristics, there are specifications.  

    tH_SDA: 0(min) 0.9us(max), it correspond to th(SDATA) on Figure71

    tPH_STA: 0.6us(min) open(max), it correspond to tw(SCLH) on Figure71

    tPL_STA: 1.3us(min) open(max), it correspond to tw(SCLL) on Figure71

     

    tH_SDA / th(SDATA) 0.9us is not the case this time, but it seems our sample device does not meet tPL_STA / tw(SCLL) specification. 

    Can we say this is damaged or defected device?

    Regards,

    Mochizuki

  • Mochizuki-san,

    I would not necessarily say that it is defective, so much as that we do not provide a maximum value for this specification (likely, it was not expected that anyone would need to have a long delay between issuing the start condition and actually writing data to the device).

    I cannot guarantee that other LMK03328 devices do not behave in the same manner - there is likely a waiting time that is not specified in the datasheet.

    I would not advise having such a long time between the start condition and data - keeping this to 100 ms or less is advised.

    Thanks,
    Kadeem

  • Hi Kadeem,

    Thank you for your support.

    When look at previous E2E thread, the designer suggested lowest SCK is 10KHz.
    e2e.ti.com/.../lmk03328-the-min-i2c-speed-of-lmk03328

    Based on this, our customer decided to utilize SCK higher than 10KHz and the other timing will follow I2C standard specification.
    To avoid any unexpected behavior on LMK03328, is this comfortable I2C setting ?


    Regards,
    Mochizuki

  • Mochizuki-san,

    So long as the frequency for I2C is above 10 kHz, and there is no long delay between the start condition and data being written to the device, there should not be an issue.

    Thanks,

    Kadeem