• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 22 subscribers
  • Views 737 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK5B12204: Jitter performance

Minghui Zhang
Prodigy 30 points

Part Number: LMK5B12204
Other Parts Discussed in Thread: LMK05318B, , LMK05318BEVM

Hello there,

LMK5B12204 has spec the jitter performance as 90 fs RMS max on pg. 14 with 48MHz input, 156.25 MHz AC-LVPECL output, may I know what's the jitter performance for 20 MHz TCXO input, 156.25 MHz AC-LVDS output?

Also datasheet spec the jitter with 48.0048 MHz input clock, may I know which part number of the osc would be recommended to achieve this jitter spec.

  • +1
    TI__Genius 17025 points

    Hi Minghui,

    Here is a plot taken on the lab bench for XO = 20 MHz (sourced from SMB100A) and OUT4 = 156.25 MHz AC-LVDS. The LMK05318B/LMK5B12204  is operating in free -run (DPLL disabled):

    The XO we used for LMK05318B/LMK5B12204 validation (how we determine the datasheet specs) is 8W48070002 , which is also put in our LMK05318BEVM and listed in the User Guide.

    If using the DPLL, we recommend XO frequencies that have a fractional relationship with VCO1 (BAW VCO) to mitigate integer boundary spurs. Common frequencies are 12.8 MHz, 19.2 MHz, 24 MHz, 30.72 MHz, 38.88 MHz, 48 MHz ,48.0048 MHz, 54 MHz.

    Regards,

    Jennifer

  • 0 in reply to Jennifer Bernal
    Prodigy 30 points

    Hi Jennifer,

    That's awesome, thanks for running the test and sharing the data! Typical RSM jitter is about the same level as 156.25 MHz with 48.0048 MHz, looks great to me. I'm happy with the 20 MHz in 156.25 MHz out with APLL1 free running mode. 

    As a further question for using the DPLL, would it be possible to have 1PPS input to PRIREF by using DPLL with the same above configuration for clock locking? If so, the recommendation is to avoid using 20 MHz XO to avoid integer boundary spurs, is my understanding correct?

  • +1 in reply to Minghui Zhang
    TI__Genius 17025 points

    Hi Minghui,

    The LMK05318B does support 1PPS input but the result with XO = 20 MHz will not be similar if DPLL is enabled.

    Please see sample plots of using XO = 20 MHz with enabled DPLL (reference frequency doesn't matter):

    • Setup
      • XO input from SMA100B
      • REF input from SML03
      • XO and REF synced

    The large spur you see at 12 kHz shifts left or right depending on the ppm accuracy. Therefore, we do not encourage XO with non-fractional relationships with VCO1.

    Regards,

    Jennifer

  • 0 in reply to Jennifer Bernal
    Prodigy 30 points

    Thank you Jennifer for sharing the data, that helps a lot! If using DPLL, I will drop 20 MHz osc and pick up one of the frequency from your recommended one. My design will use either TCXO or OCXO with high accuracy, say, 38.88 MHz with 0.28 ppm stability. However, those osc comes with 3.3V, e.g LFTCXO085780  (38.88 MHz) https://www.mouser.com/datasheet/2/741/IQD_11_21_2022_LFTCXO085780-3075066.pdf  Therefore, a voltage divider circuit would be required (125 ohm vs. 375 ohm) on the XO input side. With this 38.88 MHz osc, I believe we can achieve the same jitter level as 48.0048 MHz osc, 60 fs typ and 90 fs max. Please correct me if my understanding is not correct. 

  • +1 in reply to Minghui Zhang
    TI__Genius 17025 points

    Yes, you are correct. We have used 38.88 MHz on our DPLLs before and also recommend that frequency. A voltage divider is required with 3.3 V LVCMOS input.

    Regards,

    Jennifer