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CDCDB800: CKPWRGD_PD# power up timing

Part Number: CDCDB800

Hi Team,

will CDCDB800 start and run correctly if it only has a pull up to VDD on the pin CKPWRGD_PD#? I did not find any timing requirement in the datasheet chapter Specifications.

Thanks.

David

  • Hi David,

    Recommended specification for CKPWRGD_PD# pin  is to keep it low (< 0.5 V) until VDD reaches its VDD minimum value. VDD minimum value is 3.3 V - 5%. If you follow that requirement than there is no timing relation between VDD and CKPWRGD_PD#. Timing depends on your VDD ramp when it reaches VDD minimum valid value. 

    You can connect CLKPWGD_PD# pin to VDD through a pull up during ramp up and its a supported use case. There is an internal 10 - 40 us counter that makes sure everything is settled before anything is sent out. This counter turns on when digital supply reaches at a certain threshold so it could account for slow supply ramp cases.

     

    Best,

    Asim