• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 22 subscribers
  • Views 607 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

LMK04821: Loop filter design tool

LMK04821: PLLatinum phase noise simulation does not match datasheet plots

Mark Whittington
Intellectual 490 points

Part Number: LMK04821

LMK04821 PLLatinum Sim phase noise nowhere close to datasheet plots.

I've attempted to emulate the ~frequency plan used in the datasheet, matching filter BW and phase margin. I've used 125MHz ref and 2GHz VCO but should make almost no difference. I've disabled ref noise and am only using PLL2 with VCO0.

The integrated phase noise is ~10x higher and dominated by PLL noise. This is a built in noise profile ("use metrics" in PLLatinum radio buttons) that comes from the tool. How can the sim tool be used to appropriately set the PLL noise so that my results in the simulation match the actuals in the datasheet?

Thanks.
Mark

  • 0
    TI__Genius 12700 points

    Hi Mike,

    What's a output format selected for PLLatinum sim?

    You can choose the output format, which defines the noise floor for the simulation. 

    To get the exact loop filter BW for the given component values, you can "Smart force selected values" for C1, C2 and R2 given in datasheet.

    There seems to be noise floor is not same as datasheet specs, when enable distribution path noise. That you can enter the value manually (given in datasheet: -162dBc/Hz).

    Then simulation data would match with the datasheet specs.

    Thanks!

    Regards,
    Ajeet Pal