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LMK04828: Jitter spec

Dhanasekaran Velusamy
Prodigy 10 points
Part Number: LMK04828

Hi,

The following clock generator (Part#: LMK04828BISQ)is used in one of our application.100MHz clock is derived for DUT.

Observation:

It is observed that the random jitter is around 700fs in our board. However, the datasheet states that "88fs RMS jitter for 12KHz to 20MHz & 91fs RMS jitter for 100Hz to 20MHz.

Schematic and Register setting details are attached.

Please review the schematic and register setting details and let us know your suggestions to reduce the jitter in our design.



Fullscreen LMK04828_REGSETTING.log Download 

***************** ECMB:LMK04828:Registers **************
RESET                 10	NA2 0	SPI_3WIRE_DIS 0x1	NA1 0	RESET 0
POWERDOWN             00	POWERDOWN 0	NA 0
ID_DEVICE_TYPE        06	ID_DEVICE_TYPE 0x6
ID_PROD_15_8          d0	ID_PROD_15_8 0xd0
ID_PROD               5b	ID_PROD 0x5b
ID_MASKREV            20	ID_MASKREV 0x20
ID_VNDR_15_8          51	ID_VNDR_15_8 0x51
ID_VNDR               04	ID_VNDR 0x4
DCLKout0_DIV          19	DCLKout0_DIV 0x19	CLKout0_1_IDL 0	CLKout0_1_ODL 0	NA 0
DCLKout2_DIV          19	DCLKout2_DIV 0x19	CLKout2_3_IDL 0	CLKout2_3_ODL 0	NA 0
DCLKout4_DIV          00	DCLKout4_DIV 0	CLKout4_5_IDL 0	CLKout4_5_ODL 0	NA 0
DCLKout6_DIV          05	DCLKout6_DIV 0x5	CLKout6_7_IDL 0	CLKout6_7_ODL 0	NA 0
DCLKout8_DIV          00	DCLKout8_DIV 0	CLKout8_9_IDL 0	CLKout8_9_ODL 0	NA 0
DCLKout10_DIV         00	DCLKout10_DIV 0	CLKout10_11_IDL 0	CLKout10_11_ODL 0	NA 0
DCLKout12_DIV         19	DCLKout12_DIV 0x19	CLKout12_13_IDL 0	CLKout12_13_ODL 0	NA 0
DCLKout0_DDLY_CNT     55	DCLKout0_DDLY_CNTL 0x5	DCLKout0_DDLY_CNTH 0x5
DCLKout2_DDLY_CNT     55	DCLKout2_DDLY_CNTL 0x5	DCLKout2_DDLY_CNTH 0x5
DCLKout4_DDLY_CNT     55	DCLKout4_DDLY_CNTL 0x5	DCLKout4_DDLY_CNTH 0x5
DCLKout6_DDLY_CNT     55	DCLKout6_DDLY_CNTL 0x5	DCLKout6_DDLY_CNTH 0x5
DCLKout8_DDLY_CNT     55	DCLKout8_DDLY_CNTL 0x5	DCLKout8_DDLY_CNTH 0x5
DCLKout10_DDLY_CNT    55	DCLKout10_DDLY_CNTL 0x5	DCLKout10_DDLY_CNTH 0x5
DCLKout12_DDLY_CNT    55	DCLKout12_DDLY_CNTL 0x5	DCLKout12_DDLY_CNTH 0x5
DCLKout0_ADLY         07	DCLKout0_MUX 0x3	DCLKout0_ALDY_MUX 0x1	DCLKout0_ALDY 0
DCLKout2_ADLY         07	DCLKout2_MUX 0x3	DCLKout2_ALDY_MUX 0x1	DCLKout2_ALDY 0
DCLKout4_ADLY         03	DCLKout4_MUX 0x3	DCLKout4_ALDY_MUX 0	DCLKout4_ALDY 0
DCLKout6_ADLY         07	DCLKout6_MUX 0x3	DCLKout6_ALDY_MUX 0x1	DCLKout6_ALDY 0
DCLKout8_ADLY         03	DCLKout8_MUX 0x3	DCLKout8_ALDY_MUX 0	DCLKout8_ALDY 0
DCLKout10_ADLY        03	DCLKout10_MUX 0x3	DCLKout10_ALDY_MUX 0	DCLKout10_ALDY 0
DCLKout12_ADLY        07	DCLKout12_MUX 0x3	DCLKout12_ALDY_MUX 0x1	DCLKout12_ALDY 0
SDCLKout1_MUX         00	SDCLKout1_HS 0	SDCLKout1_DDLY 0	SDCLKout1_MUX 0	DCLKout0_HS 0	NA 0
SDCLKout3_MUX         00	SDCLKout3_HS 0	SDCLKout3_DDLY 0	SDCLKout3_MUX 0	DCLKout2_HS 0	NA 0
SDCLKout5_MUX         00	SDCLKout5_HS 0	SDCLKout5_DDLY 0	SDCLKout5_MUX 0	DCLKout4_HS 0	NA 0
SDCLKout7_MUX         00	SDCLKout7_HS 0	SDCLKout7_DDLY 0	SDCLKout7_MUX 0	DCLKout6_HS 0	NA 0
SDCLKout9_MUX         00	SDCLKout9_HS 0	SDCLKout9_DDLY 0	SDCLKout8_MUX 0	DCLKout8_HS 0	NA 0
SDCLKout11_MUX        00	SDCLKout11_HS 0	SDCLKout11_DDLY 0	SDCLKout11_MUX 0	DCLKout10_HS 0	NA 0
SDCLKout13_MUX        00	SDCLKout13_HS 0	SDCLKout13_DDLY 0	SDCLKout13_MUX 0	DCLKout12_HS 0	NA 0
SDCLKout1_ADLY        00	SDCLKout1_ADLY 0	SDCLKout1_ADLY_EN 0	NA 0
SDCLKout3_ADLY        00	SDCLKout3_ADLY 0	SDCLKout3_ADLY_EN 0	NA 0
SDCLKout5_ADLY        00	SDCLKout5_ADLY 0	SDCLKout5_ADLY_EN 0	NA 0
SDCLKout7_ADLY        00	SDCLKout7_ADLY 0	SDCLKout7_ADLY_EN 0	NA 0
SDCLKout9_ADLY        00	SDCLKout9_ADLY 0	SDCLKout9_ADLY_EN 0	NA 0
SDCLKout11_ADLY       00	SDCLKout11_ADLY 0	SDCLKout11_ADLY_EN 0	NA 0
SDCLKout13_ADLY       00	SDCLKout13_ADLY 0	SDCLKout13_ADLY_EN 0	NA 0
DCLKout0_DDLY_PD      60	SDCLKout1_PD 0	SDCLKout1_DIS_MODE 0	CLKout0_1_PD 0	DCLKout0_ADLY_PD 0	DCLKout0_ADLYg_PD 0x1	DCLKout0_HSg_PD 0x1	DCLKout0_DDLY_PD 0
DCLKout2_DDLY_PD      60	SDCLKout3_PD 0	SDCLKout3_DIS_MODE 0	CLKout2_3_PD 0	DCLKout2_ADLY_PD 0	DCLKout2_ADLYg_PD 0x1	DCLKout2_HSg_PD 0x1	DCLKout2_DDLY_PD 0
DCLKout4_DDLY_PD      68	SDCLKout5_PD 0	SDCLKout5_DIS_MODE 0	CLKout4_5_PD 0x1	DCLKout4_ADLY_PD 0	DCLKout4_ADLYg_PD 0x1	DCLKout4_HSg_PD 0x1	DCLKout4_DDLY_PD 0
DCLKout6_DDLY_PD      70	SDCLKout7_PD 0	SDCLKout7_DIS_MODE 0	CLKout6_7_PD 0	DCLKout6_ADLY_PD 0x1	DCLKout6_ADLYg_PD 0x1	DCLKout6_HSg_PD 0x1	DCLKout6_DDLY_PD 0
DCLKout8_DDLY_PD      68	SDCLKout9_PD 0	SDCLKout9_DIS_MODE 0	CLKout8_9_PD 0x1	DCLKout8_ADLY_PD 0	DCLKout8_ADLYg_PD 0x1	DCLKout8_HSg_PD 0x1	DCLKout8_DDLY_PD 0
DCLKout10_DDLY_PD     68	SDCLKout11_PD 0	SDCLKout11_DIS_MODE 0	CLKout10_11_PD 0x1	DCLKout10_ADLY_PD 0	DCLKout10_ADLYg_PD 0x1	DCLKout10_HSg_PD 0x1	DCLKout10_DDLY_PD 0
DCLKout12_DDLY_PD     60	SDCLKout13_PD 0	SDCLKout13_DIS_MODE 0	CLKout12_13_PD 0	DCLKout12_ADLY_PD 0	DCLKout12_ADLYg_PD 0x1	DCLKout12_HSg_PD 0x1	DCLKout12_DDLY_PD 0
SDCLKout1_POL         06	DCLKout0_FMT 0x6	DCLKout0_POL 0	SDCLKout1_FMT 0	SDCLKout1_POL 0
SDCLKout3_POL         06	DCLKout2_FMT 0x6	DCLKout2_POL 0	SDCLKout3_FMT 0	SDCLKout3_POL 0
SDCLKout5_POL         00	DCLKout4_FMT 0	DCLKout4_POL 0	SDCLKout5_FMT 0	SDCLKout5_POL 0
SDCLKout7_POL         06	DCLKout6_FMT 0x6	DCLKout6_POL 0	SDCLKout7_FMT 0	SDCLKout7_POL 0
SDCLKout9_POL         00	DCLKout8_FMT 0	DCLKout8_POL 0	SDCLKout9_FMT 0	SDCLKout9_POL 0
SDCLKout11_POL        00	DCLKout10_FMT 0	DCLKout10_POL 0	SDCLKout11_FMT 0	SDCLKout11_POL 0
SDCLKout13_POL        06	DCLKout12_FMT 0x6	DCLKout12_POL 0	SDCLKout13_FMT 0	SDCLKout13_POL 0
VCO_MUX               04	OSCout_FMT 0x4	OSCout_MUX 0	VCO_MUX 0	NA 0
SYSREF_MUX            00	SYSREF_MUX 0	NA 0
SYSREF_DIV_12_8       0c	SYSREF_DIV_12_8 0xc	NA 0
SYSREF_DIV_7_0        00	SYSREF_DIV_7_0 0
SYSREF_DDLY_12_8      00	SYSREF_DDLY_12_8 0	NA 0
SYSREF_DDLY_7_0       08	SYSREF_DDLY_7_0 0x8
SYSREF_PULSE_CNT      03	NA 0	SYSREF_PULSE_CNT 0x3
PLL2_NCLK_MUX         00	NA 0	PLL2_NCLK_MUX 0	PLL1_NCLK_MUX 0	FB_MUX 0	FB_MUX_EN 0
PLL1_PD               07	PLL1_PD 0	VCO_LDO_PD 0	VCO_PD 0	OSCin_PD 0	SYSREF_GBL_PD 0	SYSREF_PD 0x1	SYSREF_DDLY_PD 0x1	SYSREF_PLSR_PD 0x1
DDLYdSYSREF_EN        00	DDLYd _SYSREF_EN 0	DDLYd12_EN 0	DDLYd10_EN 0	DDLYd8_EN 0	DDLYd6_EN 0	DDLYd4_EN 0	DDLYd2_EN 0	DDLYd0_EN 0
DDLYd_STEP_CNT        00	NA 0	DDLYd_STEP_CNT 0
SYSREF_CLR            91	SYSREF_CLR 0x1	SYNC_1SHOT_EN 0	SYNC_POL 0	SYNC_EN 0x1	SYNC_PLL2_DLD 0	SYNC_PLL1_DLD 0	SYNC_MODE 0x1
SYNC_DISX             00	SYNC_DISSYSREF 0	SYNC_DIS12 0	SYNC_DIS10 0	SYNC_DIS8 0	SYNC_DIS6 0	SYNC_DIS4 0	SYNC_DIS2 0	SYNC_DIS0 0
FIXED_REGISTER        00	Fixed_Register 0
CLKin2_EN             18	NA 0	CLKin2_EN 0	CLKin1_EN 0x1	CLKin0_EN 0x1	CLKin2_TYPE 0	CLKin1_TYPE 0	CLKin0_TYPE 0
CLKin_SEL_POL         3a	CLKin_SEL_POL 0	CLKin_SEL_MODE 0x3	CLKin1_OUT_MUX 0x2	CLKin0_OUT_MUX 0x2
CLKin_SEL0_MUX        02	NA 0	CLKin_SEL0_MUX 0	CLKin_SEL0_TYPE 0x2
CLKin_SEL1_MUX        33	NA 0	SDIO_RDBK_TYPE 0	CLKin_SEL1_MUX 0x6	CLKin_SEL1_TYPE 0x3
RESET_MUX             02	NA 0	RESET_MUX 0	RESET_TYPE 0x2
LOS_TIMEOUT           16	LOS_TIMEOUT 0	LOS_EN 0	TRACK_EN 0x1	HOLDOVER_FORCE 0	MAN_DAC_EN 0x1	MAN_DAC_9_8 0x2
MAN_DAC_9_8           16	LOS_TIMEOUT 0	LOS_EN 0	TRACK_EN 0x1	HOLDOVER_FORCE 0	MAN_DAC_EN 0x1	MAN_DAC_9_8 0x2
MAN_DAC_7_0           00	MAN_DAC_7_0 0
DAC_TRIP_LOW          00	NA 0	DAC_TRIP_LOW 0
DAC_CLK_MULT          00	DAC_CLK_MULT 0	DAC_TRIP_HIGH 0
DAC_CLK_CNTR          7f	DAC_CLK_CNTR 0x7f
HOLDOVER_PLL1_DET     03	NA 0	HOLDOVER_PLL1_DET 0	HOLDOVER_LOS_DET 0	HOLDOVER_VTUNE_DET 0	HOLDOVER_HITLESS_SWITCH 0x1	HOLDOVER_EN 0x1
HOLDOVER_DLD_CNT_13_8  02	NA 0	HOLDOVER_DLD_CNT_13_8 0x2
HOLDOVER_DLD_CNT_7_0  00	HOLDOVER_DLD_CNT_7_0 0
CLKin0_R_13_8         00	NA 0	CLKin0_R_13_8 0
CLKin0_R_7_0          78	CLKin0_R_7_0 0x78
CLKin1_R_13_0         00	NA 0	CLKin1_R_13_8 0
CLKin1_R_7_0          96	CLKin1_R_7_0 0x96
CLKin2_R_13_8         00	NA 0	CLKin2_R_13_8 0
CLKin2_R_7_0          96	CLKin2_R_7_0 0
PLL1_N_13_8           00	NA 0	PLL1_N_13_8 0
PLL1_N_7_0            78	PLL1_N_7_0 0x78
PLL1_WND_SIZE         d4	PLL1_WND_SIZE 0x3	PLL1_CP_TRI 0	PLL1_CP_POL 0x1	PLL1_CP_GAIN 0x4
PLL1_DLD_CNT_13_8     20	NA 0	PLL1_DLD_CNT_13_8 0x20
PLL1_DLD_CNT_7_0      00	PLL1_DLD_CNT_7_0 0
PLL1_R_DLY            00	NA 0	PLL1_R_DLY 0	PLL1_N_DLY 0
PLL1_LD_MUX           0e	PLL1_LD_MUX 0x1	PLL1_LD_TYPE 0x6
PLL2_R_11_8           00	NA 0	PLL2_R_11_8 0
PLL2_R_7_0            02	PLL2_R_7_0 0x2
PLL2_P                44	PLL2_P 0x2	OSCin_FREQ 0x1	PLL2_XTAL_EN 0	PLL2_REF_2X_EN 0
PLL2_N_CAL_17_16      00	NA 0	PLL2_N_CAL_17_16 0
PLL2_N_CAL_15_8       00	PLL2_N_CAL_15_8 0
PLL2_N_CAL_7_0        0c	PLL2_N_CAL_7_0 0xc
PLL2_N_17_16          00	NA 0	PLL2_FCAL_DIS 0	PLL2_N_17_16 0
PLL2_N_15_8           00	PLL2_N_15_8 0
PLL2_N_7_0            19	PLL2_N_7_0 0x19
PLL2_WND_SIZE         59	NA 0	PLL2_WND_SIZE 0x2	PLL2_CP_GAIN 0x3	PLL2_CP_POL 0	PLL2_CP_TRI 0	Fixed Value 0x1
PLL2_DLD_CNT_13_8     20	NA 0	SYSREF_REQ_EN 0	PLL2_DLD_CNT_13_8 0x20
PLL2_DLD_CNT_7_0      00	PLL2_DLD_CNT 0
PLL2_LF_R4            00	NA 0	PLL2_LF_R4 0	PLL2_LF_R3 0
PLL2_LF_C4            00	PLL2_LF_C4 0	PLL2_LF_C3 0
PLL2_LD_MUX           13	PLL2_LD_MUX 0x2	PLL2_LD_TYPE 0x3
PLL2_PRE_PD           00	NA 0	PLL2_PRE_PD 0	PLL2_PD 0	NA 0
OPT_REG_1             15	OPT_REG_1 0x15
OPT_REG_2             33	OPT_REG_2 0x33
RB_PLL1_LD_LOST       00	NA 0	RB_PLL1_LD_LOST 0	RB_PLL1_LD 0	CLR_PLL1_LD_LOST 0
RB_PLL2_LD_LOST       06	NA 0	RB_PLL2_LD_LOST 0x1	RB_PLL2_LD 0x1	CLR_PLL2_LD_LOST 0
RB_DAC_VALUE_MSB      90	RB_DAC_VALUE_9_8 0x2	RB_CLKin2_SEL 0	RB_CLKin1_SEL 0x1	RB_CLKin0_SEL 0	NA 0	RB_CLKin1_LOS 0	RB_CLKin0_LOS 0
RB_DAC_VALUE          00	RB_DAC_VALUE_7_0 0
RB_HOLDOVER           10	NA 0	RB_HOLDOVER 0x1	NA 0
SPI_LOCK_23_16        00	SPI_LOCK_23_16 0
SPI_LOCK_15_8         00	SPI_LOCK_15_8 0
SPI_LOCK_7_0          00	SPI_LOCK_7_0 0


***************** ECMB:LMK04828 **************
RESET                 10	NA2 0	SPI_3WIRE_DIS 0x1	NA1 0	RESET 0
POWERDOWN             00	POWERDOWN 0	NA 0
ID_DEVICE_TYPE        06	ID_DEVICE_TYPE 0x6
ID_PROD_15_8          d0	ID_PROD_15_8 0xd0
ID_PROD               5b	ID_PROD 0x5b
ID_MASKREV            20	ID_MASKREV 0x20
ID_VNDR_15_8          51	ID_VNDR_15_8 0x51
ID_VNDR               04	ID_VNDR 0x4
DCLKout0_DIV          19	DCLKout0_DIV 0x19	CLKout0_1_IDL 0	CLKout0_1_ODL 0	NA 0
DCLKout2_DIV          19	DCLKout2_DIV 0x19	CLKout2_3_IDL 0	CLKout2_3_ODL 0	NA 0
DCLKout4_DIV          00	DCLKout4_DIV 0	CLKout4_5_IDL 0	CLKout4_5_ODL 0	NA 0
DCLKout6_DIV          05	DCLKout6_DIV 0x5	CLKout6_7_IDL 0	CLKout6_7_ODL 0	NA 0
DCLKout8_DIV          00	DCLKout8_DIV 0	CLKout8_9_IDL 0	CLKout8_9_ODL 0	NA 0
DCLKout10_DIV         00	DCLKout10_DIV 0	CLKout10_11_IDL 0	CLKout10_11_ODL 0	NA 0
DCLKout12_DIV         19	DCLKout12_DIV 0x19	CLKout12_13_IDL 0	CLKout12_13_ODL 0	NA 0
DCLKout0_DDLY_CNT     55	DCLKout0_DDLY_CNTL 0x5	DCLKout0_DDLY_CNTH 0x5
DCLKout2_DDLY_CNT     55	DCLKout2_DDLY_CNTL 0x5	DCLKout2_DDLY_CNTH 0x5
DCLKout4_DDLY_CNT     55	DCLKout4_DDLY_CNTL 0x5	DCLKout4_DDLY_CNTH 0x5
DCLKout6_DDLY_CNT     55	DCLKout6_DDLY_CNTL 0x5	DCLKout6_DDLY_CNTH 0x5
DCLKout8_DDLY_CNT     55	DCLKout8_DDLY_CNTL 0x5	DCLKout8_DDLY_CNTH 0x5
DCLKout10_DDLY_CNT    55	DCLKout10_DDLY_CNTL 0x5	DCLKout10_DDLY_CNTH 0x5
DCLKout12_DDLY_CNT    55	DCLKout12_DDLY_CNTL 0x5	DCLKout12_DDLY_CNTH 0x5
DCLKout0_ADLY         07	DCLKout0_MUX 0x3	DCLKout0_ALDY_MUX 0x1	DCLKout0_ALDY 0
DCLKout2_ADLY         07	DCLKout2_MUX 0x3	DCLKout2_ALDY_MUX 0x1	DCLKout2_ALDY 0
DCLKout4_ADLY         03	DCLKout4_MUX 0x3	DCLKout4_ALDY_MUX 0	DCLKout4_ALDY 0
DCLKout6_ADLY         07	DCLKout6_MUX 0x3	DCLKout6_ALDY_MUX 0x1	DCLKout6_ALDY 0
DCLKout8_ADLY         03	DCLKout8_MUX 0x3	DCLKout8_ALDY_MUX 0	DCLKout8_ALDY 0
DCLKout10_ADLY        03	DCLKout10_MUX 0x3	DCLKout10_ALDY_MUX 0	DCLKout10_ALDY 0
DCLKout12_ADLY        07	DCLKout12_MUX 0x3	DCLKout12_ALDY_MUX 0x1	DCLKout12_ALDY 0
SDCLKout1_MUX         00	SDCLKout1_HS 0	SDCLKout1_DDLY 0	SDCLKout1_MUX 0	DCLKout0_HS 0	NA 0
SDCLKout3_MUX         00	SDCLKout3_HS 0	SDCLKout3_DDLY 0	SDCLKout3_MUX 0	DCLKout2_HS 0	NA 0
SDCLKout5_MUX         00	SDCLKout5_HS 0	SDCLKout5_DDLY 0	SDCLKout5_MUX 0	DCLKout4_HS 0	NA 0
SDCLKout7_MUX         00	SDCLKout7_HS 0	SDCLKout7_DDLY 0	SDCLKout7_MUX 0	DCLKout6_HS 0	NA 0
SDCLKout9_MUX         00	SDCLKout9_HS 0	SDCLKout9_DDLY 0	SDCLKout8_MUX 0	DCLKout8_HS 0	NA 0
SDCLKout11_MUX        00	SDCLKout11_HS 0	SDCLKout11_DDLY 0	SDCLKout11_MUX 0	DCLKout10_HS 0	NA 0
SDCLKout13_MUX        00	SDCLKout13_HS 0	SDCLKout13_DDLY 0	SDCLKout13_MUX 0	DCLKout12_HS 0	NA 0
SDCLKout1_ADLY        00	SDCLKout1_ADLY 0	SDCLKout1_ADLY_EN 0	NA 0
SDCLKout3_ADLY        00	SDCLKout3_ADLY 0	SDCLKout3_ADLY_EN 0	NA 0
SDCLKout5_ADLY        00	SDCLKout5_ADLY 0	SDCLKout5_ADLY_EN 0	NA 0
SDCLKout7_ADLY        00	SDCLKout7_ADLY 0	SDCLKout7_ADLY_EN 0	NA 0
SDCLKout9_ADLY        00	SDCLKout9_ADLY 0	SDCLKout9_ADLY_EN 0	NA 0
SDCLKout11_ADLY       00	SDCLKout11_ADLY 0	SDCLKout11_ADLY_EN 0	NA 0
SDCLKout13_ADLY       00	SDCLKout13_ADLY 0	SDCLKout13_ADLY_EN 0	NA 0
DCLKout0_DDLY_PD      60	SDCLKout1_PD 0	SDCLKout1_DIS_MODE 0	CLKout0_1_PD 0	DCLKout0_ADLY_PD 0	DCLKout0_ADLYg_PD 0x1	DCLKout0_HSg_PD 0x1	DCLKout0_DDLY_PD 0
DCLKout2_DDLY_PD      60	SDCLKout3_PD 0	SDCLKout3_DIS_MODE 0	CLKout2_3_PD 0	DCLKout2_ADLY_PD 0	DCLKout2_ADLYg_PD 0x1	DCLKout2_HSg_PD 0x1	DCLKout2_DDLY_PD 0
DCLKout4_DDLY_PD      68	SDCLKout5_PD 0	SDCLKout5_DIS_MODE 0	CLKout4_5_PD 0x1	DCLKout4_ADLY_PD 0	DCLKout4_ADLYg_PD 0x1	DCLKout4_HSg_PD 0x1	DCLKout4_DDLY_PD 0
DCLKout6_DDLY_PD      70	SDCLKout7_PD 0	SDCLKout7_DIS_MODE 0	CLKout6_7_PD 0	DCLKout6_ADLY_PD 0x1	DCLKout6_ADLYg_PD 0x1	DCLKout6_HSg_PD 0x1	DCLKout6_DDLY_PD 0
DCLKout8_DDLY_PD      68	SDCLKout9_PD 0	SDCLKout9_DIS_MODE 0	CLKout8_9_PD 0x1	DCLKout8_ADLY_PD 0	DCLKout8_ADLYg_PD 0x1	DCLKout8_HSg_PD 0x1	DCLKout8_DDLY_PD 0
DCLKout10_DDLY_PD     68	SDCLKout11_PD 0	SDCLKout11_DIS_MODE 0	CLKout10_11_PD 0x1	DCLKout10_ADLY_PD 0	DCLKout10_ADLYg_PD 0x1	DCLKout10_HSg_PD 0x1	DCLKout10_DDLY_PD 0
DCLKout12_DDLY_PD     60	SDCLKout13_PD 0	SDCLKout13_DIS_MODE 0	CLKout12_13_PD 0	DCLKout12_ADLY_PD 0	DCLKout12_ADLYg_PD 0x1	DCLKout12_HSg_PD 0x1	DCLKout12_DDLY_PD 0
SDCLKout1_POL         06	DCLKout0_FMT 0x6	DCLKout0_POL 0	SDCLKout1_FMT 0	SDCLKout1_POL 0
SDCLKout3_POL         06	DCLKout2_FMT 0x6	DCLKout2_POL 0	SDCLKout3_FMT 0	SDCLKout3_POL 0
SDCLKout5_POL         00	DCLKout4_FMT 0	DCLKout4_POL 0	SDCLKout5_FMT 0	SDCLKout5_POL 0
SDCLKout7_POL         06	DCLKout6_FMT 0x6	DCLKout6_POL 0	SDCLKout7_FMT 0	SDCLKout7_POL 0
SDCLKout9_POL         00	DCLKout8_FMT 0	DCLKout8_POL 0	SDCLKout9_FMT 0	SDCLKout9_POL 0
SDCLKout11_POL        00	DCLKout10_FMT 0	DCLKout10_POL 0	SDCLKout11_FMT 0	SDCLKout11_POL 0
SDCLKout13_POL        06	DCLKout12_FMT 0x6	DCLKout12_POL 0	SDCLKout13_FMT 0	SDCLKout13_POL 0
VCO_MUX               04	OSCout_FMT 0x4	OSCout_MUX 0	VCO_MUX 0	NA 0
SYSREF_MUX            00	SYSREF_MUX 0	NA 0
SYSREF_DIV_12_8       0c	SYSREF_DIV_12_8 0xc	NA 0
SYSREF_DIV_7_0        00	SYSREF_DIV_7_0 0
SYSREF_DDLY_12_8      00	SYSREF_DDLY_12_8 0	NA 0
SYSREF_DDLY_7_0       08	SYSREF_DDLY_7_0 0x8
SYSREF_PULSE_CNT      03	NA 0	SYSREF_PULSE_CNT 0x3
PLL2_NCLK_MUX         00	NA 0	PLL2_NCLK_MUX 0	PLL1_NCLK_MUX 0	FB_MUX 0	FB_MUX_EN 0
PLL1_PD               07	PLL1_PD 0	VCO_LDO_PD 0	VCO_PD 0	OSCin_PD 0	SYSREF_GBL_PD 0	SYSREF_PD 0x1	SYSREF_DDLY_PD 0x1	SYSREF_PLSR_PD 0x1
DDLYdSYSREF_EN        00	DDLYd _SYSREF_EN 0	DDLYd12_EN 0	DDLYd10_EN 0	DDLYd8_EN 0	DDLYd6_EN 0	DDLYd4_EN 0	DDLYd2_EN 0	DDLYd0_EN 0
DDLYd_STEP_CNT        00	NA 0	DDLYd_STEP_CNT 0
SYSREF_CLR            91	SYSREF_CLR 0x1	SYNC_1SHOT_EN 0	SYNC_POL 0	SYNC_EN 0x1	SYNC_PLL2_DLD 0	SYNC_PLL1_DLD 0	SYNC_MODE 0x1
SYNC_DISX             00	SYNC_DISSYSREF 0	SYNC_DIS12 0	SYNC_DIS10 0	SYNC_DIS8 0	SYNC_DIS6 0	SYNC_DIS4 0	SYNC_DIS2 0	SYNC_DIS0 0
FIXED_REGISTER        00	Fixed_Register 0
CLKin2_EN             18	NA 0	CLKin2_EN 0	CLKin1_EN 0x1	CLKin0_EN 0x1	CLKin2_TYPE 0	CLKin1_TYPE 0	CLKin0_TYPE 0
CLKin_SEL_POL         3a	CLKin_SEL_POL 0	CLKin_SEL_MODE 0x3	CLKin1_OUT_MUX 0x2	CLKin0_OUT_MUX 0x2
CLKin_SEL0_MUX        02	NA 0	CLKin_SEL0_MUX 0	CLKin_SEL0_TYPE 0x2
CLKin_SEL1_MUX        33	NA 0	SDIO_RDBK_TYPE 0	CLKin_SEL1_MUX 0x6	CLKin_SEL1_TYPE 0x3
RESET_MUX             02	NA 0	RESET_MUX 0	RESET_TYPE 0x2
LOS_TIMEOUT           16	LOS_TIMEOUT 0	LOS_EN 0	TRACK_EN 0x1	HOLDOVER_FORCE 0	MAN_DAC_EN 0x1	MAN_DAC_9_8 0x2
MAN_DAC_9_8           16	LOS_TIMEOUT 0	LOS_EN 0	TRACK_EN 0x1	HOLDOVER_FORCE 0	MAN_DAC_EN 0x1	MAN_DAC_9_8 0x2
MAN_DAC_7_0           00	MAN_DAC_7_0 0
DAC_TRIP_LOW          00	NA 0	DAC_TRIP_LOW 0
DAC_CLK_MULT          00	DAC_CLK_MULT 0	DAC_TRIP_HIGH 0
DAC_CLK_CNTR          7f	DAC_CLK_CNTR 0x7f
HOLDOVER_PLL1_DET     03	NA 0	HOLDOVER_PLL1_DET 0	HOLDOVER_LOS_DET 0	HOLDOVER_VTUNE_DET 0	HOLDOVER_HITLESS_SWITCH 0x1	HOLDOVER_EN 0x1
HOLDOVER_DLD_CNT_13_8  02	NA 0	HOLDOVER_DLD_CNT_13_8 0x2
HOLDOVER_DLD_CNT_7_0  00	HOLDOVER_DLD_CNT_7_0 0
CLKin0_R_13_8         00	NA 0	CLKin0_R_13_8 0
CLKin0_R_7_0          78	CLKin0_R_7_0 0x78
CLKin1_R_13_0         00	NA 0	CLKin1_R_13_8 0
CLKin1_R_7_0          96	CLKin1_R_7_0 0x96
CLKin2_R_13_8         00	NA 0	CLKin2_R_13_8 0
CLKin2_R_7_0          96	CLKin2_R_7_0 0
PLL1_N_13_8           00	NA 0	PLL1_N_13_8 0
PLL1_N_7_0            78	PLL1_N_7_0 0x78
PLL1_WND_SIZE         d4	PLL1_WND_SIZE 0x3	PLL1_CP_TRI 0	PLL1_CP_POL 0x1	PLL1_CP_GAIN 0x4
PLL1_DLD_CNT_13_8     20	NA 0	PLL1_DLD_CNT_13_8 0x20
PLL1_DLD_CNT_7_0      00	PLL1_DLD_CNT_7_0 0
PLL1_R_DLY            00	NA 0	PLL1_R_DLY 0	PLL1_N_DLY 0
PLL1_LD_MUX           0e	PLL1_LD_MUX 0x1	PLL1_LD_TYPE 0x6
PLL2_R_11_8           00	NA 0	PLL2_R_11_8 0
PLL2_R_7_0            02	PLL2_R_7_0 0x2
PLL2_P                44	PLL2_P 0x2	OSCin_FREQ 0x1	PLL2_XTAL_EN 0	PLL2_REF_2X_EN 0
PLL2_N_CAL_17_16      00	NA 0	PLL2_N_CAL_17_16 0
PLL2_N_CAL_15_8       00	PLL2_N_CAL_15_8 0
PLL2_N_CAL_7_0        0c	PLL2_N_CAL_7_0 0xc
PLL2_N_17_16          00	NA 0	PLL2_FCAL_DIS 0	PLL2_N_17_16 0
PLL2_N_15_8           00	PLL2_N_15_8 0
PLL2_N_7_0            19	PLL2_N_7_0 0x19
PLL2_WND_SIZE         59	NA 0	PLL2_WND_SIZE 0x2	PLL2_CP_GAIN 0x3	PLL2_CP_POL 0	PLL2_CP_TRI 0	Fixed Value 0x1
PLL2_DLD_CNT_13_8     20	NA 0	SYSREF_REQ_EN 0	PLL2_DLD_CNT_13_8 0x20
PLL2_DLD_CNT_7_0      00	PLL2_DLD_CNT 0
PLL2_LF_R4            00	NA 0	PLL2_LF_R4 0	PLL2_LF_R3 0
PLL2_LF_C4            00	PLL2_LF_C4 0	PLL2_LF_C3 0
PLL2_LD_MUX           13	PLL2_LD_MUX 0x2	PLL2_LD_TYPE 0x3
PLL2_PRE_PD           00	NA 0	PLL2_PRE_PD 0	PLL2_PD 0	NA 0
OPT_REG_1             15	OPT_REG_1 0x15
OPT_REG_2             33	OPT_REG_2 0x33
RB_PLL1_LD_LOST       00	NA 0	RB_PLL1_LD_LOST 0	RB_PLL1_LD 0	CLR_PLL1_LD_LOST 0
RB_PLL2_LD_LOST       06	NA 0	RB_PLL2_LD_LOST 0x1	RB_PLL2_LD 0x1	CLR_PLL2_LD_LOST 0
RB_DAC_VALUE_MSB      90	RB_DAC_VALUE_9_8 0x2	RB_CLKin2_SEL 0	RB_CLKin1_SEL 0x1	RB_CLKin0_SEL 0	NA 0	RB_CLKin1_LOS 0	RB_CLKin0_LOS 0
RB_DAC_VALUE          00	RB_DAC_VALUE_7_0 0
RB_HOLDOVER           10	NA 0	RB_HOLDOVER 0x1	NA 0
SPI_LOCK_23_16        00	SPI_LOCK_23_16 0
SPI_LOCK_15_8         00	SPI_LOCK_15_8 0
SPI_LOCK_7_0          00	SPI_LOCK_7_0 0
LMK04828_CLOCK SECTION.pdf

Thank you,
Dhanasekaran.V

  • 0
    TI__Mastermind 18950 points

    Hi Dhanasekaran,

    Thanks for the information, I have paged our jitter cleaner expert.

    Best,

    Evan Su

  • 0 in reply to Evan Su
    Prodigy 10 points

    Hi Evan Su,

    Thanks for your update.

    Some more observations

    1. Since external oscillator has been connected with Oscin pin of clock gen, we understand that single loop has been implemented in our design. Therefore, PLL1 has not been used. Please review our schematic and confirm it.

    2. Random Jitter measurement has been taken with various frequency (from lower frequency to higher frequency). Rj is higher at lower frequencies and lower at higher frequencies (Ex: 192fs @ 250MHz, 133fs @ 1250MHz). Rj is getting increased while "N" of PLL2 getting increased.

    Regards,

    Dhanasekaran.V

  • 0 in reply to Dhanasekaran Velusamy
    TI__Mastermind 18950 points

    Hi Dhanasekaran,

    Dhanasekaran Velusamy said:
    1. Since external oscillator has been connected with Oscin pin of clock gen, we understand that single loop has been implemented in our design. Therefore, PLL1 has not been used. Please review our schematic and confirm it.

    I looked at your schematic and it appeared to line up with the single loop mode. To be sure I would need to check the full device configuration. I reviewed the .log file you provided but I am not familiar with the format and could not find some of the registers I was looking for such as OSCin_PD. Did you use our TICS Pro software to generate the register configuration? If so, please provide us with an exported configuration file (.tcs), it will help us review the situation more quickly.

    Our expert seems to have been busy yesterday but I hope he will be able to get back to you soon.

    Best,

    Evan Su

  • 0 in reply to Evan Su
    Prodigy 10 points

    Hi Evan,

    The register setting value is 0x07. Therefore, OSCin_PD bit is "0". 

    PLL1_PD- 07 PLL1_PD 0 VCO_LDO_PD 0 VCO_PD 0 OSCin_PD 0 SYSREF_GBL_PD 0 SYSREF_PD 0x1 SYSREF_DDLY_PD 0x1 SYSREF_PLSR_PD 0x1

    Regards,

    Dhanasekaran.V

  • 0 in reply to Dhanasekaran Velusamy
    TI__Mastermind 18950 points

    Hi Dhanasekaran,

    After opening the log file in a different IDE, I was able to search it more efficiently. I will review the PLL configuration as best I can but optimizing for jitter is beyond my abilities, so if our expert has not replied by next week I will check with him.

    Thanks,

    Evan Su

  • 0 in reply to Evan Su
    Prodigy 10 points

    Hi Evan Su,

    I have not received any updates on this. It is very urgent. 

    Please provide the register setting for dual loop mode.

    Thank you,

    Regards,

    Dhanasekaran.V

  • 0 in reply to Dhanasekaran Velusamy
    TI__Genius 12560 points

    Hi Dhanasekaran,

    Please allow me sometime. I'll respond you shortly today.

    Thanks!

    Regards,
    Ajeet Pal

  • 0 in reply to Ajeet Pal
    TI__Genius 12560 points

    Hi Dhanasekaran,

    Are you performing the test with on-board VCXO (U7) or external input at OSCIN_N pin?

    If it is through U7, C279 should be DNI and OSCIN_N pin connect to GND through C280.

    If the reference is external at OSCIN_N pin, U7 should be power down, which can introduce lot of spurs on the output and you would see worst jitter number. Also you need to keep C353 as 0.1uF, C352 as DNI and R227 replace with 0ohm resistor.

    To use in the dual PLL loop, you need to have external input at CLKin0/1/2 input pins for the PLL1. But there is no input pins are connected to any connector for external input. Hence, it can't be configure in dual PLL mode.

    Thanks!

    Regards,

    Ajeet Pal

  • 0 in reply to Ajeet Pal
    Prodigy 10 points

    Hi Ajeet Pal,

    Thank you for your feedback.

    We have another board with various input clock options. We would like to configure it in dual loop mode. Could you provide the register setting.

    Regards,

    Dhanasekaran.V

  • 0 in reply to Dhanasekaran Velusamy
    TI__Genius 12560 points

    Hi Dhanasekaran,

    Can you please share the CLKin0/CLKin1 input frequency to PLL1 and used VCXO frequency to generate the config file for you?

    Thanks!

    Regards,

    Ajeet Pal

  • 0 in reply to Ajeet Pal
    Prodigy 10 points

    HI Ajeet Pal,

    Input frequency is 50MHz/100MHz. VCXO is 50MHz.

    Thank you,

    Regards,

    Dhanasekaran.V

  • 0 in reply to Dhanasekaran Velusamy
    TI__Genius 12560 points

    Hi Dhanasekaran,

    Please see below configuration file for the CLKin1 input 50MHz and VCXO 50MHz settings.


    LMK04828_dual_loop.tcs

    For the required output, you can change the clock divider values.

    Thanks!

    Regards,

    Ajeet Pal

  • 0 in reply to Ajeet Pal
    Prodigy 10 points

    Hi Ajeet Pal,

    Thank you,

    We will try it and let you know.

    Regards,

    Dhanasekaran.V

  • 0 in reply to Dhanasekaran Velusamy
    Prodigy 10 points

    Dear Ajeet Pal,

    We have done few test cases to measure the Jitter level in the LMK04828 Evaluation board designed by TI. The test reports are attached.

    Observation: 

    1. The datasheet states that 88fs RMS Jitter (12KHz to 20MHz) & 91fs RMS Jitter (100Hz to 20 MHz). However, we are observing more than the datasheet spec.  Please clarify the test condition at which TI observed 88fs & 91fs. 

    2. Jitter value is high at low frequencies and low at the high frequencies. It shows that jitter is getting varied based on the divider value. Please clarify it.

    3. Is any correlation between Input OCSInp, Internal VCO0 or VCO1, Divider value used to configure the desired clock out at the DCKOUTxP&N with minimal jitter. 

    4. The datasheet states that Jitter would be optimized for the dual loop mode. However, we did not notice much difference between single loop and dual loop. Please clarify.

    5. We would like to generate 100MHz (Differential) clock out with 50MHz & 100MHz clockin with dual mode & single mode. Please provide the setting for this condition. 

    6. Do you have jitter spec for 100MHz diff clock out?.

    Thank you

    Regards,

    Dhanasekaran.V

  • 0 in reply to Dhanasekaran Velusamy
    TI__Genius 12560 points

    Hi Dhanasekaran,

    Dhanasekaran Velusamy said:
    1. The datasheet states that 88fs RMS Jitter (12KHz to 20MHz) & 91fs RMS Jitter (100Hz to 20 MHz). However, we are observing more than the datasheet spec.  Please clarify the test condition at which TI observed 88fs & 91fs. 

    What are the configuration used for phase noise testing? Please share the used configuration file.

    You can use the default configuration "CLKin1 122.88MHz, OSCin 122.88MHz" available in TICS pro and set the CLKout0/2 port for required frequency. also make SYNC_DISx --> "1". It should give  the optimized phase noise measured data.

    Dhanasekaran Velusamy said:
    2. Jitter value is high at low frequencies and low at the high frequencies. It shows that jitter is getting varied based on the divider value. Please clarify it.

    The jitter numbers at lower output frequencies are not coming true. At higher divider values, there is less change at far off noise, hence it may increase the total jitter, which can  be in the range of ~100-120fsec even at divider value 32. May be you can look on the measurement setup.

    Dhanasekaran Velusamy said:
    3. Is any correlation between Input OCSInp, Internal VCO0 or VCO1, Divider value used to configure the desired clock out at the DCKOUTxP&N with minimal jitter. 

    Yes, with the higher phase detector frequency, the N-divider would be less and improve the overall flat noise performance and have optimized/improved jitter.

    Dhanasekaran Velusamy said:
    4. The datasheet states that Jitter would be optimized for the dual loop mode. However, we did not notice much difference between single loop and dual loop. Please clarify.

    The dual loop mode operates as jitter cleaner, where input at the PLL1 may be noisy and using the optimized PLL1 setting and used VCXO, the over all jitter performance can be improved. In your case, PLL1 may be already with optimized phase detector frequency and loop filter BW and the PLL2 output would see the VCXO performance at close-in offset in both the cases. Hence, it shows the almost came performance.

    Dhanasekaran Velusamy said:
    5. We would like to generate 100MHz (Differential) clock out with 50MHz & 100MHz clockin with dual mode & single mode. Please provide the setting for this condition

    LMK04828EVM has the on-board VCXO frequency 122.88MHz. Hence we could not have  the optimized phase noise number for 100MHz output, which would required the integer multiple of VCXO frequency for higher phase detector frequencies. 

    If you would have the setup, I can help to provide the configuration settings FYR.

    Thanks!

    Regards,
    Ajeet Pal

  • 0 in reply to Ajeet Pal
    Prodigy 10 points

    Hi  Ajeet Pal,

    Thank you for your feedback..

    Random Jitter was measured with low N divider value (PLL2 R & N divider- 1 & 12) (Refer attached doc: LMK04828_Jitter Measurement_15thJune2023). Register setting has been extracted from TICSPRO and attached here. However, the jitter is more than 300fs.

    Our End customer is worried about jitter. Expected random jitter should be less than 200fs @ 100MHz clock out in any D clock out channels.

    Therefore, we are requesting TI to suggest register setting in detail .i.e Clkin range, PLL1 Rdivider, PLL2 Rdivider, PLL2 N divider, PLL2 N Prescaler, etc.. to derive the 100MHz output clock with less than 200fs Random jitter.

    LMK04828_Jitter_Measurement_15thJune2023.xlsx

    Fullscreen HexRegisterValues_2400.txt Download 
    R0 (INIT)	0x000090
R0	0x000000
R2	0x000200
R3	0x000300
R4	0x000400
R5	0x000500
R6	0x000600
R12	0x000C00
R13	0x000D00
R256	0x010000
R257	0x010100
R258	0x010200
R259	0x010300
R260	0x010400
R261	0x010500
R262	0x010600
R263	0x010700
R264	0x010800
R265	0x010900
R266	0x010A00
R267	0x010B00
R268	0x010C00
R269	0x010D00
R270	0x010E00
R271	0x010F00
R272	0x011000
R273	0x011100
R274	0x011200
R275	0x011300
R276	0x011400
R277	0x011500
R278	0x011600
R279	0x011700
R280	0x011800
R281	0x011900
R282	0x011A00
R283	0x011B00
R284	0x011C00
R285	0x011D00
R286	0x011E00
R287	0x011F00
R288	0x012000
R289	0x012100
R290	0x012200
R291	0x012300
R292	0x012400
R293	0x012500
R294	0x012600
R295	0x012700
R296	0x012838
R297	0x012900
R298	0x012A00
R299	0x012B00
R300	0x012C00
R301	0x012D00
R302	0x012E00
R303	0x012F06
R304	0x013000
R305	0x013100
R306	0x013200
R307	0x013300
R308	0x013400
R309	0x013500
R310	0x013600
R311	0x013700
R312	0x013800
R313	0x013900
R314	0x013A00
R315	0x013B00
R316	0x013C00
R317	0x013D00
R318	0x013E00
R319	0x013F00
R320	0x014000
R321	0x014100
R322	0x014200
R323	0x014300
R324	0x014400
R325	0x014500
R326	0x014600
R327	0x014700
R328	0x014800
R329	0x014900
R330	0x014A00
R331	0x014B00
R332	0x014C00
R333	0x014D00
R334	0x014E00
R335	0x014F00
R336	0x015000
R337	0x015100
R338	0x015200
R339	0x015300
R340	0x015400
R341	0x015500
R342	0x015600
R343	0x015700
R344	0x015800
R345	0x015900
R346	0x015A00
R347	0x015B00
R348	0x015C00
R349	0x015D00
R350	0x015E00
R351	0x015F00
R352	0x016000
R353	0x016100
R354	0x016280
R355	0x016300
R356	0x016400
R357	0x016500
R369	0x017100
R370	0x017200
R380	0x017C00
R381	0x017D00
R358	0x016600
R359	0x016700
R360	0x01680C
R361	0x016900
R362	0x016A00
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E00
R371	0x017300
R386	0x018200
R387	0x018300
R388	0x018400
R389	0x018500
R392	0x018800
R393	0x018900
R394	0x018A00
R395	0x018B00
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF00
    Fullscreen 8154.HexRegisterValues_2500.txt Download 
    R0 (INIT)	0x000090
R0	0x000000
R2	0x000200
R3	0x000300
R4	0x000400
R5	0x000500
R6	0x000600
R12	0x000C00
R13	0x000D00
R256	0x010000
R257	0x010100
R258	0x010200
R259	0x010300
R260	0x010400
R261	0x010500
R262	0x010600
R263	0x010700
R264	0x010800
R265	0x010900
R266	0x010A00
R267	0x010B00
R268	0x010C00
R269	0x010D00
R270	0x010E00
R271	0x010F00
R272	0x011000
R273	0x011100
R274	0x011200
R275	0x011300
R276	0x011400
R277	0x011500
R278	0x011600
R279	0x011700
R280	0x011800
R281	0x011900
R282	0x011A00
R283	0x011B00
R284	0x011C00
R285	0x011D00
R286	0x011E00
R287	0x011F00
R288	0x012000
R289	0x012100
R290	0x012200
R291	0x012300
R292	0x012400
R293	0x012500
R294	0x012600
R295	0x012700
R296	0x012839
R297	0x012900
R298	0x012A00
R299	0x012B00
R300	0x012C00
R301	0x012D00
R302	0x012E00
R303	0x012F0E
R304	0x013000
R305	0x013100
R306	0x013200
R307	0x013300
R308	0x013400
R309	0x013500
R310	0x013600
R311	0x013700
R312	0x013800
R313	0x013900
R314	0x013A00
R315	0x013B00
R316	0x013C00
R317	0x013D00
R318	0x013E00
R319	0x013F00
R320	0x014000
R321	0x014100
R322	0x014200
R323	0x014300
R324	0x014400
R325	0x014500
R326	0x014600
R327	0x014700
R328	0x014800
R329	0x014900
R330	0x014A00
R331	0x014B00
R332	0x014C00
R333	0x014D00
R334	0x014E00
R335	0x014F00
R336	0x015000
R337	0x015100
R338	0x015200
R339	0x015300
R340	0x015400
R341	0x015500
R342	0x015600
R343	0x015700
R344	0x015800
R345	0x015900
R346	0x015A00
R347	0x015B00
R348	0x015C00
R349	0x015D00
R350	0x015E00
R351	0x015F00
R352	0x016000
R353	0x016100
R354	0x0162A0
R355	0x016300
R356	0x016400
R357	0x016500
R369	0x017100
R370	0x017200
R380	0x017C00
R381	0x017D00
R358	0x016600
R359	0x016700
R360	0x01680A
R361	0x016900
R362	0x016A00
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E00
R371	0x017300
R386	0x018200
R387	0x018300
R388	0x018400
R389	0x018500
R392	0x018800
R393	0x018900
R394	0x018A00
R395	0x018B00
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF00
    Fullscreen HexRegisterValues_3000.txt Download 
    R0 (INIT)	0x000090
R0	0x000000
R2	0x000200
R3	0x000300
R4	0x000400
R5	0x000500
R6	0x000600
R12	0x000C00
R13	0x000D00
R256	0x010000
R257	0x010100
R258	0x010200
R259	0x010300
R260	0x010400
R261	0x010500
R262	0x010600
R263	0x010700
R264	0x010800
R265	0x010900
R266	0x010A00
R267	0x010B00
R268	0x010C00
R269	0x010D00
R270	0x010E00
R271	0x010F00
R272	0x011000
R273	0x011100
R274	0x011200
R275	0x011300
R276	0x011400
R277	0x011500
R278	0x011600
R279	0x011700
R280	0x011800
R281	0x011900
R282	0x011A00
R283	0x011B00
R284	0x011C00
R285	0x011D00
R286	0x011E00
R287	0x011F00
R288	0x012000
R289	0x012100
R290	0x012200
R291	0x012300
R292	0x012400
R293	0x012500
R294	0x012600
R295	0x012700
R296	0x01283E
R297	0x012900
R298	0x012A00
R299	0x012B00
R300	0x012C00
R301	0x012D00
R302	0x012E00
R303	0x012F0E
R304	0x013000
R305	0x013100
R306	0x013200
R307	0x013300
R308	0x013400
R309	0x013500
R310	0x013600
R311	0x013700
R312	0x013820
R313	0x013900
R314	0x013A00
R315	0x013B00
R316	0x013C00
R317	0x013D00
R318	0x013E00
R319	0x013F00
R320	0x014000
R321	0x014100
R322	0x014200
R323	0x014300
R324	0x014400
R325	0x014500
R326	0x014600
R327	0x014700
R328	0x014800
R329	0x014900
R330	0x014A00
R331	0x014B00
R332	0x014C00
R333	0x014D00
R334	0x014E00
R335	0x014F00
R336	0x015000
R337	0x015100
R338	0x015200
R339	0x015300
R340	0x015400
R341	0x015500
R342	0x015600
R343	0x015700
R344	0x015800
R345	0x015900
R346	0x015A00
R347	0x015B00
R348	0x015C00
R349	0x015D00
R350	0x015E00
R351	0x015F00
R352	0x016000
R353	0x016100
R354	0x016280
R355	0x016300
R356	0x016400
R357	0x016500
R369	0x017100
R370	0x017200
R380	0x017C00
R381	0x017D00
R358	0x016600
R359	0x016700
R360	0x01680F
R361	0x016900
R362	0x016A00
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E00
R371	0x017300
R386	0x018200
R387	0x018300
R388	0x018400
R389	0x018500
R392	0x018800
R393	0x018900
R394	0x018A00
R395	0x018B00
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF00

    Regards,

    Dhanasekaran.V

    LMK04828_Jitter_Measurement_15thJune2023.xlsx

  • 0 in reply to Dhanasekaran Velusamy
    TI__Genius 12560 points

    Hi Dhanasekaran,

    Thanks for sharing the details measured data.

    Here, I would be suspecting the measurement error/issue in your setup. As the shared measured data with 100MHz VCXO, it can't be quick compare and I would suggest to verify the measurement data using the LMK04828EVM at the datasheet given frequencies (245.76MHz) using VCO0 and VCO1.

    Below is the quick measured data on LMK04828EVM at 245.76MHz using VCO1 with the default configuration mentioned in previous response. Here, the noise floor is around -160dBc/Hz, whereas your measured data have noise floor bit higher (>5dB) and there is direct jump in the phase noise at 1MHz offset. This could be the measurement instrument limitation. 

    You can try to change the instrument (Agilent E5052B or R&S FSWP, etc..) and see the performance. 

    LMK04828 surely can provide the output jitter better than 200ps.

    Thanks!

    Regards,
    Ajeet Pal