LMK1D1204: clock buffer solution recommendation: 1 single end input, 1 differential signal output, 125Mhz clock buffer.

Ken,

The LMK1D210x is LVDS fan-out buffer with dual inputs which fan-out to dual outputs banks. Each input can fan-out to a maximum of four outputs; whereas the single bank device LMK1D1204.

For the LMKD210x device, you are able input two separate clocks into bank one or the other to fanout two.four total outputs each, whereas the LMK1D receives one input to fanout to four outputs. 

What are your exact requirements? How many signals do you want to fanout? How many end points do you want to fanout the signal to?

Patton,

    Pls ignore above requirement.

    customer now needs the attached clock generator solutions. Can you give any suggestion?

Note:  if A device can support all clock outputs in clock generator 1 (or in generator 2). It is preferred.

if one clock generator can't support all  clock outputs in  1(or generator 2), pls recommend a device to support clock generator 3 (or 4).

clock-spec.pptx

Zhang,

If you would like to look into our CDCE6214, I believe we will be able to meet your requirements. 

CDCE6214 Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs, Two Inputs, and Internal EEPROM datasheet