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CDCLVC1310: schematic check&some question

ALEX jack
Prodigy 20 points
Part Number: CDCLVC1310

Hello

1、schematic check

      We use CDCLVC1310 as CLK BUFFER，The clock input and output circuits are shown in the following figure，please help check if the circuit is correct.

      The detailed information of the circuit is as follows:

     (1)TCXO VPP=800mV（±400mV),clipped sine ，frequency is 76.8MHZ,

     (2)76.8MHZ is a single end CLK

     (3) We connnected the clipped sine clock of 76.8MHZ to PRI_IN

     (3)Need to convert clipped sine to LVCMOS(0~1V8)

2、In addition，About  CDCLVC1310 ，I also have some question to ask for advice,

     Single-end DC characteristic  min( VIH-VIL)=0.7V，so how dose the chip achieve wing of 0.15V.

  • +1
    TI__Genius 9250 points

    Hi Alex,

    ALEX jack said:
    schematic check

    Schematic biasing is correct as mentioned above. It should be okay. One thing I that you want to make sure that this clipped sine wave is above the the threshold limits specified otherwise it would cause duty cycle distortion. Sine wave could cause this behavior because you slowly rise to peak voltage and it reaches threshold voltage at peak. So your switching time gets narrowed due to that. This shows up usually when dealing with small swings.

    ALEX jack said:

    In addition，About  CDCLVC1310 ，I also have some question to ask for advice,

         Single-end DC characteristic  min( VIH-VIL)=0.7V，so how dose the chip achieve wing of 0.15V.

    Differential to single conversion of  a differential amplifier is not perfect so we usually characterize the single ended mode in our test and come up with these safe threshold values for single ended operation.  For differential case, we can even get switching with smaller thresholds hence you can get away with even smaller swings.

    Let me know if you have any additional concerns.

    Best,

    Asim

  • 0 in reply to Asim Khan
    Prodigy 20 points

    hello

         there is  one more question that I need to consult with,  In the design above ，the TCXO slew rate is 

    Rising slew rate:449mv/ns
    Rising slew rate：-353mV/ns

         Does this result meet the chip requirements

            

  • 0 in reply to ALEX jack
    TI__Genius 9250 points

    Hi Alex,

    It is well below the typical value of 2V/ns recommended in the datasheet. I think it should still work but you might not get the best performance in terms of electrical specs. Unfortunately, I don't have test data for what the minimum spec is supported. 

    Best,

    Asim