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CDCE6214: Jitter, PPM, pF/Rise Time, pF/Fall Time

Daniel Hoasov Cohen
Intellectual 320 points

Part Number: CDCE6214
Other Parts Discussed in Thread: TMS320C6655

Hi,

According to the datasheet, it's not so clear to find parameter the below, I would appreciate it if you could help me with this:

1. Clock Jitter?

2. Clock PPM?

3. Load capacitance [pF] of Rise Time and Fall Time?

also, will that Programmable CLK Gen fit to Gauss DSP TMS320C6655 clocks: Coreclk, DDRclk & SRIOSGMIIclk?

  • +1
    TI__Mastermind 18780 points

    Hi Daniel,

    I see this is related to the TMS320C6655 question from earlier.

    Daniel Hoasov Cohen said:
    Clock Jitter?

    This is the summary from the first page.

    Daniel Hoasov Cohen said:
    Clock PPM?

    Maximum frequency error when in fractional PLL mode is 0.1 ppm. I have no other data available but I believe that you can assume 0.1 ppm maximum for the device as a whole.

    Daniel Hoasov Cohen said:
    Load capacitance [pF] of Rise Time and Fall Time?

    Output rise/fall times are in the output characteristics sections of the datasheet (7.17, 7.18, 7.19) . Load capacitance data is available for the crystal in section 7.8 but I am not sure if that is what you are talking about.

    I have no other information on the TMS320C6655 clocks, so that discussion can be continued on your original thread in the Processors forum.

    Thanks,

    Evan Su