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LMX2594: LMX2594 Digital IO compatibility standards

Part Number: LMX2594

Hi,

In my design Four LMX2594 Devices are connected to Virtex Ultrascale + 11P device. In Virtex 11P device, we do not have any HD Banks, only HP Bank (1V8) are available.
So the Digital interface from the LMX2594(SLK, SDI, CSB, CE, RampDir, RampClk, MUXout, SYNC (CMOS Mode), SysRefReq (CMOS Mode) lines need to be level translate to the 3V logic level, but in datasheet It is mentioned that CSB, SCLK, SDI are 1.8-V to 3.3-V logic. and CE, RampDir, RampClk, MUXout, SYNC (CMOS Mode), SysRefReq (CMOS Mode) supporting 1V8 Logic level as the electrical characteristics.
If I want to connect these lines how to FPGA, How to do?
Issue-1: If I use Level translator from Logic 1V8 to Logic 3V3 level then VOL of Level translator is of 0.7V @3.3V whereas VIL of LMX Device is 0.4V, in this case I cannot use Level translator.
Can I directly connect CSB, SCLK, SDI, CE, RampDir, RampClk, SYNC, SysRefReq signals from FPGA 1V8 Logic and can I use 1V8 to 3V3 Level translator only for MuxOUT signal?