Original question:
LMX2491: How to use PLLatinum sim design LMX2491 Loop filter （extern VCO and extern divider）
Hello
I try to design a 24GHz RF frontend based on the LMX2491 in combination with a 24GHz VCO what has an integrated divide by 16 output. There is a limitation of the Fvco from 500 to 6400 MHz what makes no sense in my opinion. I can use 24000 MHz in the Fvco field but it will get red marked.
Does this red marking mean that it is not possible with this PLL?
Hello Noel
Thanks for your answer but I'm quiet sure that this will work. I saw different designs using the LMX2491 in 24GHz FMCW radars. I use a VCO at 24GHz with a divide by 16 output -> The RF input of the PLL will be around 1.5GHz. I've tried to setup the PLL like this but always get a red alert:
How can I setup the PLL to work with an external VCO with an external Prescaler?
Hi Ueli,
OK, now I know what is your problem.
The schematic diagram is not correct, I have informed the developer to fix it, there should be no divider in the diagram.
Anyway, you can still use it to proceed the design as long as don't use the upper divider.
or you can make VCO frequency = 1.5GHz and scale down Kvco accordingly. This way, we won't see any error.
