LMK1C1102: t1G_ON/t1G_OFF minimum

David

Part Number: LMK1C1102

t1G_ON and t1G_OFF are specified as maximum cycles (5), with no minimum. Are there conditions where this is the guaranteed minimum as well? i.e., setup time, hold time, specific frequencies?

I would like to use this part as part of a data pipeline, but I need any cycle delay for the synchronous enable to be fixed.

over 2 years ago

0 Asim Khan over 2 years ago

TI__Genius 9260 points

Hi David,

You can get a minimum 2 cycle delay, when your clock rising edge comes soon after the 1G rise. But we don't have any characterization data for this specific case, that's why there is no minimum specification in the datasheet.

Best,

Asim

0 David over 2 years ago in reply to Asim Khan

Prodigy 10 points

Thanks. If the input itself is synchronous and arrives mid-cycle, will the delay consistently be the maximum (5)?

+1 Asim Khan over 2 years ago in reply to David

TI__Genius 9260 points

Hi David,

I don't think you would achieve it consistently to be maximum 5 cycles. There two flip flops in series to synchronize the 1G input to clock input. You could have 2 to 3 clock cycle plus the internal buffer delay.

Best,

Asim

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LMK1C1102: t1G_ON/t1G_OFF minimum