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LMK04826: SPI Interface Timing

JH Shin
Guru 11110 points
Part Number: LMK04826

Hello,

My customer has questions about the LMK04826 SPI interface timing.

Here is the SPI interface timing table in the LMK04826 datasheet

Q1 ) SCLK's period specification is MIN 50nS(20MHz). When the customer uses 20MHz as SCLK, they are concerned about insufficient margin.

        Would there be any problem using 20MHz? Please also explain why.

Q2 ) SCLK's High/Low width specification is MIN 25nS. When the customer uses 20MHz as SCLK, if the High:Low ratio is not 5:5, one side will be less than 25nS. Is this a problem?

Thank you.

JH

  • 0
    TI__Mastermind 33720 points

    JH,

    1) No problem with 20MHz. Every device is production tested with >20MHz SPI bus, and characterization guarantees substantial timing margin on the SPI interface (almost an order of magnitude faster). I think this is just a weird specification by TI, because we did not clearly outline the meaning of "high width" and "low width". The diagram implies these apply to >50% of VCC and <50% of VCC respectively, but this is probably not the best measure. It is probably better to say the "high width" extends from the positive threshold crossing of VIH to the negative threshold crossing of VIL, and "low width" extends from the negative threshold crossing of VIL to the positive threshold crossing of VIH.

    In any case, I think we are trying to convey that a 20MHz clock with about 50% duty cycle is okay, or a 10MHz clock with 25% duty cycle is okay, and so on.

    2) Note that the data setup and hold times are listed as 10ns minimum each. Taking this as guidance, I'd say 50 ± 10% duty cycle is acceptable for SCLK at 20MHz, with the duty cycle error being a function of either slew rate limitations or some variable pulse width. Below 20MHz there is no significant duty cycle limitation beyond the minimum high width and low width.

    Please convey to customer that we have tested this bus over PVT at much higher than 20MHz with no issues, so minor variations in 50% duty cycle or allowances for rise/fall time are not going to be an issue. THIGH = 20ns or TLOW = 20ns is not going to prevent SPI communication.

    Regards,

    Derek Payne