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Sundance CDCM7005 M/N Settings

imranulhaq qureshi
Prodigy 30 points
Other Parts Discussed in Thread: CDCM7005

Dear All,

I m using Sundance ADC/DAC smt350 Module which is equiped with CDCM7005,all the default settings work fine.

 It can be used for Internal and Extenal Clock mode.

Internal Clock mode settings are

   1.FB_MUX    = 0x4 means P-Devider =6;

   2.M-Devider  = 0x1F3 = 499

   3.N-Devider  = 0xF7F = 3967

   4.VCXO   =  245.76Mhz

   5.Refrence Clock   =  10Mhz

I want to give

External Clock      = 80Mhz (replacement of VCXO)

 Reference clock  = 10Mhz 

Kindly tell me How to calculate (NxP) / M so that CDCM7005 should Lock to 80Mhz external clock

N=?

M=?

Thanx in Advance

Regards

Imran

 

  • 0
    TI__Expert 3985 points

    hi Imran,

    thanks a lot for your interest in our device. In order to better support you, let me please ask you for some further info. Are you planning to use the same 245.76MHz VCXO to generate a 80MHz output?

    Thanks a lot,

    Regards,

    Leandro

  • 0 in reply to Leandro_z
    Prodigy 30 points

    Hi Leandro,

    Thanx for your support, Actually current system has two modes of operation

    1. Internal Mode: in this mode internal VCXO of 245.76 is connected with CDCM7005.

    2.External Mode:in this mode External clock Source(Agilent Function generator) is used to give 80Mhz clock signal to CDCM7005.

    Rgds

    Imran

  • 0 in reply to imranulhaq qureshi
    TI__Expert 3985 points

    Hi Imran,

    the CDCM7005 is a jitter cleaner. Basically it generates an output clock whose jitter is lower than the jitter of reference clock. In order to do that, a feedback system is required. In the CDCM7005 some blocks (PFD, Charge Pump, M N and P dividers) of this system are integrated; some other blocks (Low Pass Filter and VCXO) need to be placed externally. If you refer to fig. 24 of datasheet, you can see that a Low Pass Filter (LPF) needs to be connected to the CP_OUT pin. The output of the LPF has to be connected to the V_CTRL pin of the VCXO in order to fine tune the VCXO output frequency. The jitter cleaning effect is reached when the signal frequency of the two signals at the PFD inputs are the same (Lock Condition). On TI website you can find a nice tool to calculate the divider settings to get the Lock Condition.

    http://focus.ti.com/docs/toolsw/folders/print/cdc-cdcm7005-calc.html

    If you use an external clock source (Agilent function generator) instead of a VCXO  and if you are not able to control/tune the external clock frequency, you use the CDCM7005 no longer as jitter cleaner but as a buffer. Therefore, we can not guarantee that the device works as specified.

    In any case, could you please send me the schematic of your system? Is the Low Pass filter disconnected during the External Mode operation?

    Best Regards,

    Leandro

  • 0 in reply to Leandro_z
    Prodigy 30 points

    Dear Leandro,

    Thanx for your detail reply,I have attached the manual of SMT350 Module just check Figure no 6.

    regards,

    Imran

    5633.SMT350_User_Manual.pdf

     

  • 0 in reply to imranulhaq qureshi
    TI__Expert 3985 points

    Hi Imran,

    thank you for providing me the SMT530 User Manual. According to it, in External Mode the CDCM7005 is supposed to act as a buffer. It will not clean the input clock signal. This means that M, N and P will have no influence, since the loop is open in this configuration. Therefore, there is no lock condition to be achieved.

    You need just to take care of the Output Divider Selection (Yx_MUX) values. They will define the division ratio between the External Clock (80MHz) and the output clocks.

    Best Regards,

    Leandro