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LMK5C33216EVM: "Loss of Phase Lock"

Yatindra Raykar
Prodigy 10 points
Part Number: LMK5C33216EVM

I want to generate a certain clock frequency and in the process, I encountered some issues. I used the attached config files to configure the LMK in TICS Pro. After loading the config file and reading back the status bits, I found that LOPL_DPLL3 is clearing and reappearing randomly when I do "Clear Latched Bits">>"Read Status". I have attached a few instances of the same.

To further verify the phase lock, I tried to find the phase difference between the clock signal generated by the LMK device and the same frequency clock signal generated by a master clock source, which also gives the reference(REF1=10MHz, REF0=100MHz) to the LMK device. It was observed that the phase difference between the two clocks varies with time.

But when the default configuration is used, the phase difference between the LMK clock and master clock is constant wrt time, and also the LOPL_DPLL3 clear on reading the status.

What is the HD2 amplitude that is expected for differential output?

LMK5C33216 config for AFE testing, boost on, config1.tcs

  • 0
    TI__Mastermind 28550 points

    Hello,

    So the latched bits, available when interrupt enable = 1 (INT_EN=1) is a great way to catch an event which may be coming and going such as an intermittent LOPL.

    One thing I've seen with LOPL is that if the reference has some high jitter and/or if the DPLL LBW is narrow, it may be necessary to increase the phase lock window threshold.  On the validation page, on right hand side you can increase the DPLL3 phase lock detect threshold size.

    • There is hysteresis hence the lock and unlock threshold size.
    • By design, when DPLL loop filter is calculated or Reassign All button is pressed, the threshold is set to a minimum value to accommodate the variations of the delta sigma DPLL.  But to allow LOPL to work for different combinations of input jitter/wander and DPLL loop bandwidth, these thresholds should be increased.

    73,
    Timothy

  • 0 in reply to Timothy T
    TI__Prodigy 10 points

    I tried to change the DLL3 phase lock detect Threshold size by. I am observing an LOFL_DPLL3 error.