• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 22 subscribers
  • Views 460 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CDCLVC1102: CDCLVC1102

Amrutha k n
Prodigy 40 points
Part Number: CDCLVC1102

HI,

Attached my design for review,

I need to give 24MHZ clock to RSCLK pin of DSP and BITCLK of CODEC, Will this design work as is?

  • 0
    TI__Mastermind 18950 points

    Hi Amrutha,

    We have paged a device expert. He will get back to you after the July 4th holiday.

    Best,

    Evan Su

  • 0 in reply to Evan Su
    TI__Genius 9260 points

    Hi Amrutha,

    Capacitive loading and series resistance can be reduce to get a proper swing. Even though the cutoff frequency is higher than your clock input. I would not use that excessive capacitive loading because rise and fall time of the signal is fast and it would result in filtering the sharp edges. You can try a 5 pF load cap value. Furthermore, the output impedance of the driver is around 45 ohm at 3.3 V. You can just add 5 ohm in series to match the transmission line impedance. 

    Let me know if this answers your question.

    Best,

    Asim