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HI,
Attached my design for review,
I need to give 24MHZ clock to RSCLK pin of DSP and BITCLK of CODEC, Will this design work as is?
Hi Amrutha,
We have paged a device expert. He will get back to you after the July 4th holiday.
Best,
Evan Su
Hi Amrutha,
Capacitive loading and series resistance can be reduce to get a proper swing. Even though the cutoff frequency is higher than your clock input. I would not use that excessive capacitive loading because rise and fall time of the signal is fast and it would result in filtering the sharp edges. You can try a 5 pF load cap value. Furthermore, the output impedance of the driver is around 45 ohm at 3.3 V. You can just add 5 ohm in series to match the transmission line impedance.
Let me know if this answers your question.
Best,
Asim