LMK04828: duty cycle of sdclkout

Do you have the SYNC_DISSYSREF bit cleared? The signal from the SYSREF divider shares a common internal routing with the signal from the SYNC system (we refer to it as the SYNC/SYSREF distribution path), so it's possible the SYSREF divider is accidentally resetting itself which could have an effect on the duty cycle. The SYNC_DISx bits gate the signal from the SYNC/SYSREF distribution path: when the SYNC_DISx bits are set to 1, the dividers will not be reset by a logic high signal on the SYNC/SYSREF distribution path. Likewise when the SYNC_DISx bits are cleared to 0, the dividers will be reset by any logic high signal on the SYNC/SYSREF distribution path (which can include the SYSREF divider - leading to some strange behavior).

Normally the duty cycle should be 50%, though I admit I haven't checked for odd divides and it may be off by one distribution path cycle.

Actually I am following the steps given in the "setup of sysref example" on page 40 of the datasheet. Thus yes I clear SYNC_DISSYSREF(0x144). The only difference between what I am doing regarding the example is that I use continous sysref at the end. How I program critical registers regarding the sysref/sync signals is given as follows:

x"143" --> x"91" sync mode is set to 1; sync_en is set to 1; sysref_clr bit is set to 1

x"144" --> x"00" sync_dissysref and all sync_disx bits are cleared

x"139" --> x"00" sysref_mux is set to normal sync

x"143" --> x"B1" sync_pol is toggled

x"143" --> x"91" syc_pol is toggled

x"144" --> x"FF" sync_dissysref and all sync_disx bits are asserted

x"143" --> x"12" sysref_clr bit is cleared to 0 and sync_mode is set to 2(it doesnt matter which mode it is though, since we are using continous sysref)

x"139" --> x"03" sysref_mux is set to continous mode

What I get at the end as sysref signal is given below. Note that I monitor sysref signal in the FPGA and even before LMK is programmed I get a logic high for sysref.

Interesting. Your procedure looks correct. Do you have the SYSREF_DDLY or the SYSREF_DIV programmed to a value < 8? Otherwise, can I just get the register programming sequence you're using? I can test this out on my own board and try to replicate the issue.

Incidentally, I just noticed you asked about the polarity of the signal - if you set the SDCLKoutY_POL bit, that should invert the polarity.

Hi,

Hi,

I am sending the register values that I use in the attachement. I have couple points to make though. I set the SYSREF_DDLY to be 8 since according to Eq-1 and Eq-2 on page 45 of the datasheet I get:

DELAY_dclk=5+5= 10 VCO cycles(VCO runs at 3GHz)

DELAY_sdclk= 8+0+2+0=10

SYSREF_DIV is set to be x"03c0"= 960 %4=0 Thus SYSREF_DIV_ADJUST=2

and 

Since DCLKoutX_MUX=0 then DCLKoutX_MUX_ADJUST=0

Is above calculation correct? I am getting perfectly aligned device clk and sysref right?

By the way since I am not using SDCLKoutY as device clock output i.e., SDCLKoutY_MUX is set to 1(SYSREF as output) changing polarity the way you described does not work right?

Thanks for your help.

x"000" , x"80"
x"000" , x"00 "
x"002" , x"00"
x"100" , x"6F "
x"101" , x"55"
x"103" , x"00"
x"104" , x"20"
x"105" , x"00"
x"106" , x"70"
x"107" , x"11"
x"108" , x"6C"
x"109" , x"55"
x"10B" , x"00"
x"10C" , x"20"
x"10D" , x"00"
x"10E" , x"73"
x"10F" , x"01"
x"110" , x"6F"
x"111" , x"55"
x"113" , x"00"
x"114" , x"20"
x"115" , x"00"
x"116" , x"73"
x"117" , x"01"
x"118" , x"01"
x"119" , x"55"
x"11B" , x"02"
x"11C" , x"20"
x"11D" , x"00"
x"11E" , x"F9"
x"11F" , x"00"
x"120" , x"01"
x"121" , x"55"
x"123" , x"02"
x"124" , x"20"
x"125" , x"00"
x"126" , x"F9"
x"127" , x"00"
x"128" , x"63"
x"129" , x"55"
x"12B" , x"00"
x"12C" , x"20"
x"12D" , x"00"
x"12E" , x"70"
x"12F" , x"16"
x"130" , x"01"
x"131" , x"55"
x"133" , x"02"
x"134" , x"20"
x"135" , x"00"
x"136" , x"F9"
x"137" , x"00"
x"138" , x"24"
x"139" , x"00"
x"13A" , x"03"
x"13B" , x"C0"
x"13C" , x"00"
x"13D" , x"08"
x"13E" , x"03"
x"13F" , x"00"
x"140" , x"80"
x"141" , x"00"
x"142" , x"00"
x"143" , x"91"
x"144" , x"00"
x"145" , x"7F"
x"146" , x"18"
x"147" , x"12"
x"148" , x"1B"
x"149" , x"5B"
x"14A" , x"02"
x"14B" , x"16"
x"14C" , x"00"
x"14D" , x"00"
x"14E" , x"C0"
x"14F" , x"7F"
x"150" , x"02"
x"151" , x"02"
x"152" , x"00"
x"153" , x"0A"
x"154" , x"00"
x"155" , x"0A"
x"156" , x"00"
x"157" , x"00"
x"158" , x"96"
x"159" , x"00"
x"15A" , x"64"
x"15B" , x"F4"
x"15C" , x"20"
x"15D" , x"00"
x"15E" , x"00"
x"15F" , x"13"
x"160" , x"00"
x"161" , x"01"
x"162" , x"44"
x"163" , x"00"
x"164" , x"00"
x"165" , x"0C"
x"171" , x"AA"
x"172" , x"02"
x"17C" , x"15"
x"17D" , x"33"
x"166" , x"00"
x"167" , x"00"
x"168" , x"0F"
x"169" , x"41"
x"16A" , x"20"
x"16B" , x"00"
x"16C" , x"00"
x"16D" , x"00"
x"16E" , x"13"
x"173" , x"00"
x"143" , x"B1"
x"143" , x"91"
x"144" , x"FF"
x"143" , x"12"
x"139" , x"02"

I hope you are not out of answers :).