LMK04821EVM 默认配置（如图1所示）下PLL2无法锁相（Status_LD2 不亮），输出时钟频率不正确
图1：
修改N Divider和N prescaler可以实现锁相（Status_LD2 亮，输出时钟频率正确可调），但VCO1 输出频率已经超出Datasheet范围，PLL2的锁相频率fpd2也不满足手册要求，配置如下图2所示：
图2：
修改Doubler 和 Divider，可以在满足VCO输出频率范围的条件下锁相（Status_LD2 亮，但输出时钟频率不正确），配置如图三所示
图3：
Hi Well, `
Can you confirm an ~122.88 MHz signal from VCXO?
Something seems off, VCO1 for LMK04821 is limited to the following frequency range:
Have you confirmed clk outputs when you the LED appears to indicate lock?
Regards,
Vicente
Hi Well,
N-cal divider should be equal to N-divider. The default configuration has set this to 12, this is the reason why PLL did not lock. Change it to 6 then you should be able to get PLL2 locked.
Hi Noel,
I change the N_Cal_Divider from 12 to 6, and still don't locked, the config as the picture.
