TLC555: Frequency deviation from set value

Hey Ryu, 

The max frequency is a typical of 2.1MHz. The minimum is 1.2MHz meaning that if you take a distribution of devices then you will see a spread of the maximum operating frequency anywhere from 1.2MHz to 2.1MHz. It is very difficult to achieve accurate results above 100kHz and you must use the equations in the PDS that account for propagation delays in order to estimate the timing. These equations are shown on page 17. I have found the propagation delays on the units I measured to be 215ns for both TPHL and TPLH. The values can vary up to 30%. 

Below you can see that there is significant curvature (non-linear) behavior at frequencies above 100kHz and the timing capacitor needs to be small for high frequencies. For this reason the tolerance of the capacitor must be well controlled and board parasitic capacitance must be accounted for. My recommendation is to use an LCR meter to measure the timing capacitor at the frequency of interest and also measure the board parasitic capacitance with the TLC555 removed from the board. This will give the most accurate result in the equations when plugging in this total capacitance for CT. My recommendation is to use these equations in excel and plugin the real measured values. In addition you should account for the tolerances of components stated from the manufacturer. The timing capacitor is critical and should be film or COG/NPO. The tolerance of the capacitor will be given as 5% in some cases but it is important to measure at the frequency of interest as well to get an accurate value to plug in.  I have attached my example calculator with some values already plugged in for demonstration such as the propagation delays and board parasitic capacitance of my board. See the excel sheet below. Lastly, in the calculator I also calculate the duty cycle at the particular frequencies. You will notice that it is roughly a 60% duty cycle in this case. 

There are some general best practice guidelines to follow for minimizing parasitic capacitance in the layout of the PCB.

1. Increasing space between adjacent traces
2. Cutting out power and ground planes above and below critical traces
3. Minimizing component to component trace lengths. Shorter traces will have less capacitance due to capacitance per unit length.
4. Minimizing use of Vias on critical traces.

TLC555 Equations (1).xlsx

Best Regards, 

Chris Featherstone