LMX2594: Improving the phase noise response?

Hello.  

I am hoping that anyone from the LMX team can answer our inquiry.

We had 2 questions about improving the phase noise of the LMX2594.

This is our setup of the phase lock loop:

1. The reference frequency for the LMX2594 is 125MHz. I want to use the LMX2594’s low noise doubler to improve the PLL noise, so the PD frequency will be 250MHz.
2. The denominator is fixed at 2^32-3 =  4,294,967,293 (no matter doubler enabled or disabled ), so that it is not dividable by 2 or 3 to avoid fractional spur.
3. We use the LMX2594’s VCO continuously from 7500MHz to 15000MHz to achieve continuous frequency coverage.

Below is an excel table of the N-divider setting at the various output frequencies that we are using (VCO frequency, PD frequency is at 250MHz, and the corresponding N divider value).

If we use MASH_ORDER = 2, due to the Minimum N limitation shown in TABLE 2 of the DATASHEET, only VCO range from 8000-15000MHz that is listed in our excel table below IS USEABLE. This is no problem since we only lose a small portion of the VCO coverage from 7500MHz to 8000MHz.

Also, I am not concerned about the PLL integer boundary spur since there exists another reference oscillator slightly different than 125MHz to use if necessary to avoid the integer boundary spur.

1^st question: For a setup where the DOUBLER is ENABLED (PD 250MHz), the DENOMINATOR of 2^32-3 =  4,294,967,293 is used, and MASH_ORDER is set to 2, will there be PLL spur degradation as compared to a setup where the DOUBLER is DISABLED (PD 125MHz), and the MASH ORDER is set to 4? Our current LMX setup does not use the doubler, and always uses MASH_ORDER =4 to avoid PLL spurs. I am very interested to use the doubler along with MASH_Order = 2. While using our current test bed, we had tried a couple of VCO frequencies with the doubler enabled and Mash_order set to 2, and we did see an improved PLL phase noise.  However due to limitations in our test setup, we are not able to investigate the PLL spurs across the full frequency range as depicted in the excel table listed below when using the lower MASH_ORDER of 2.  Do you have any idea what is expected in terms of the PLL Spur degradation across our range of operation?  Does the Spur degration get worst by using the doubler in combination with Mash_order =2?

2^nd question: We also want to possibly use MASH_ORDER = 3, but we are limited by the Minimum N divider restrictions as shown in TABLE 2 of the DATASHEET.  Is there a more detailed explanation of the Minimum N divider rule based on VCO frequency range? Is there any way to loosen this rule for the Minimum N divider value when setting MASH_ORDER to 3?

Any response to the 2 questions above will be greatly appreciated.

Thanks