Hi,
I plan to lock DPLL3 to 1pps (1Hz) at IN0_P port of the eval board. I use APLL3 with external XO of 100MHz to produce 156.25MHz HSDS output at port 4. APLL3 locked well to 100MHz XO independent to DPLL3 status. Somehow, DPLL did not lock DPLL3 to 1pps signal at status page while it locks to 25MHz. I also tried 1MHz reference to DPLL and it locked well. I tried 0.1MHz reference signal but it failed to lock DPLL3. It looks like it does not lock below 1MHz while datasheet said it accepts from 0.5Hz. FYI, I used Matlab Runtime script for DPLL settings for all cases. Can you please recommend what shall I try to make this work?
Thanks,
Youngho