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CDCM7005-SP: Recommended termination for unused pins

Kazuhiko Hirano
Genius 13968 points
Part Number: CDCM7005-SP

Hello,

Q1:
My customer would like to use CDCM7005-SP as just a clock divider/distributor, not a PLL as follows.
Single-ended frequency input to VCXO_IN to P Divider to YXA/Bs. So, the following PINs are not used.
For those unused PINs, what kind of terminations are recommended? Or can those PINs be left floating?
  CP_OUT(8pin)
  REF_SEL(12pin)
  PRI_REF(14pin)
  SEC_REF(15pin)
  STATUS_VCXO or I_REF_CP(49pin)
  STATUS_REF or PRI_SEC_CLK(50pin)
  PLL_LOCK(52pin)

Q2:
Datasheet “6 Pin Configuration and Functions” says PLL_LOCK is I/O pin. However, the PLL_LOCK pin is always output in the other datasheet descriptions. Under what cases, could PLL_LOCK pin acts as an input pin? Or the “I/O” is just typo in the datasheet?

Best regards,

K.Hirano

  • 0
    TI__Genius 12560 points

    Hi Hirano-san,

    This is called buffer mode. Unfortunately, there is no ability to pin-strap register settings. Programming the SPI would be required, unless the default config is appropriate.

    Since buffer mode will not need the charge pump, VCC_CP can be grounded to minimize current consumption.
    CP_OUT can be left floating. No need to program it from default in configuration. If you choose to bias to gnd through pulldown, then it would be necessary to program CP_OUT to tristate in configuration.

    Best solution for the reference inputs (PRI_REF, SEC_REF, REF_SEL) would be to use pullups to VCC. They are weakly pulled up internally, so adding external pullups minimizes power, and stabilizes quicker.

    STATUS_VCXO or I_REF_CP pin can keep floating or can use for the status of the VCXO_IN input signal.

    As not using the PRI and SEC clocks, can keep the  STATUS_REF or PRI_SEC_CLK in floating for not status of reference clocks.

    PLL_LOCK pin is seems to be output pin only and can be left floating. I can check internally from design side and confirm on this typo. 



    Thanks!

    Regards,

    Ajeet Pal