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LMK5B33216: Synthesizing a 133.33MHz using APPL2

Ali Ghorashi
Prodigy 71 points
Part Number: LMK5B33216


I'm trying to generate a 133.33MHz clock on outputs 4,5,and 6 using an LMK5B33216EVM evaluation board. I have the APLL2 using the BAW as its reference. I have the channel dividers set to 21 and the APPL2 post divider set to 2. The plan is to use an APLL2 frequency of 5599.86MHz and divide the output by 42 to get 133.33MHz.

But when I look at the LVDS output of channel 4, I get a frequency of 138.98MHz instead of 133.33MHz. That means that APLL2 is running at 138.98 x 42 = 5837.16MHz instead of 5599.86MHz.

 I have tried using an APPL2 frequency of 5600MHz and got the same results. I have also tried using a PLL frequency of 5866.2 and divide by 44. In that case, I get an output frequency of 132.66MHz which implies that the PLL is running at 44x132.66MHz=5837.04MHz instead of 5866.2MHz.

All the clocks that feed of APLL3 work correctly. Here are my configurations. I'm not using the DPLL. I have also attached my TICS PRO configuration if someone wants to look at it.

LMK5B_tics_pro.tcs

  • 0
    TI__Expert 3135 points

    Hello Ali,

    The calculation of VCO and dividers are correct to get 133.33 MHz. However, I see your PLL2 PDF referencing VCO3 at 2500 MHz PDF. VCO1 and VCO2 can have max PDF at 125 MHz. Please change to this setting and re-run the VCO calculation again.

    Please also check on a few these things:

    1. if you're not using 48-MHz onboard TCXO, please ensure the input to XO is 48 MHz

    2. on the Status page, are both LOS_FDET_XO and LOL_PLL2 low? LOL_PLL2 would ensure VCO2 is active and generating the output

    Let me know if this works.

    -Riley

  • 0 in reply to Riley Nguyen
    Prodigy 71 points

    Thank you Riley. I did try that before my post and it did not help. I ended up doing a soft reset of the chip and that fixed problem. For some reason, when I change various output stage value values in the GUI, they take effect right away on the evaluation board via register writes performed by the program. But the PLL settings won't change until you do a soft reset (??). This had me chasing my tail for a day and half.

    So the workaround sequence of actions is:

    1. Power up the evaluation board
    2. Write all the registers (note: at this point the APPL2 frequency will be wrong)
    3. Do a soft reset (note: at this point APPL2 will lock to the correct frequency)

    Do you know why ? Is there a better way?

    Thanks

    -Ali

  • +1 in reply to Ali Ghorashi
    TI__Expert 3135 points

    Hi Ali,

    When you change PLL settings, it is necessary to ensure the changes on the calculated VCO frequencies and dividers are written to the device by doing "Write all registers" and "Soft-reset chip".

    The proper actions after powering up device and load your config would be:

    - Follow these sequence to get the correct VCO and dividers for the target outputs

    - Then do "Write all registers" and "Soft-reset chip".

    - Check Status to ensure PLLs are locked.

    -Riley