LMK5B12204: LMK5B12204 DPLL not Locked

1055.lmk.tcs

Here is the .tcs file. Sorry I didn't upload it earlier.

Hi Javier,

Thanks for the TCS, we'll check and advise.

73,
Timothy

I did a quick look at your schematic - I don't see any big issues... however I would have suggested placing a 33 ohm series resistor at output as a source termination for the LVCMOS output.  Then have the voltage divider close to the IC.  I imagine the distances you have probably this doesn't cause an issue.

-- Also, about your locking issue.  Did you try staring with the 1-PPS Default configuration?

Is your input validated?

Note that 1-PPS phase detector should be enabled along with validation timer, all other validations off.  The ppm error between input and XO must be small, even with the max 63 setting on 1-PPS phase detector.

73,
Timothy

I do not know what you mean by starting with the 1-PPS default configuration.

However, I did read registers R14, R167, and R411.

R14 I read the following: 0xD0. It seems the DPLL doesn't exit from a holdover event as the DPLL doesn't lock to frequency or phase.

When I read register R167 I get the following: 0x00

When I read register R411 I get the following: 0x00

I'm not sure how to interpret as the user programming guide doesn't have any information about those registers.

Was there any problem with the tics file I sent over?

Thanks,

Javier

Hi Javier, 

1. The DPLL won't lock unless the reference gets validated (PRIREFVAL_STAT, R411[2]). Getting this bit to set is the first step in the debug.If it's clear, the device will remain in holdover and the outputs stay locked to the XO input.

2. To elaborate on Timothy's comment with the reference vallidation:

   When configuring a 1-PPS input, only the 1-PPS Phase Detector and Validation Timer can be enabled for reference validation.

   The phase detector sets the XO accuracy through the PRIREF_PH_VALID_THR register. The counter has a maximum value of 63.

   If XO exceeds required accuracy, then the 1-PPS reference will not be detected.

   • • Equation:
       • XO accuracy [ppm] = PRIREF_PH_VALID_THR / XO frequency [MHz]
     • Example 1:
       • XO = 20 MHz
       • PRIREF_PH_VALID_THR  = 63, maximize XO accuracy range
       • Required XO accuracy = ± 3.15 ppm
     • Example 2:
       • XO = 12.8 MHz
       • PRIREF_PH_VALID_THR  = 63, maximize XO accuracy range
       • Required XO accuracy = ± 4.92 ppm
       • We recommend 12.8 MHz XO input for 1-PPS applications.

What is the accuracy of your XO? For the reference to validate, it should be less than 3 ppm.

Regards,

Jennifer

Thank you. I've purchased a new XO at 12.8MHz with ±2ppm accuracy. It should arrive in a few days. I hope to have an update soon.

Thank you. Please keep me posted.

Hello,

The new XO has arrived. It is 12.8MHz with ±2.5ppm frequency stability.
https://www.digikey.com/en/products/detail/jauch-quartz/O-12-80-JT32C-A-K-3-3-LF/8107804

I changed the .tcs file because I added the new XO: 3463.lmk.tcs

I read registers R13, R14, R167, and R411 to get the following:

R13: 0x1D
R14: 0xC0
R167: 0x2
R411: 0x8

To answer your initial question, here is the setting of the reference:

Any help would be greatly appreciated.

Hi Javier,

Please try with this .tcs file. I've set OUT2/3 to 10 MHz CMOS. The DPLL settings are configured for 1-PPS PRIREF using a 12.8 MHz XO input.

LMK5B12204_DPLL LBW=0.01 Hz_XO=12.8 MHz_PRIREF=1PPS_OUT23=10 MHz_Oct 3 2023.tcs

Regards,

Jennifer

Looks like we are onto something here!

Reading the same registers we have the following:
R13: 0x0
R14: 0xC0
R167: 0x1
R411: 0x4

Looks like now the reference is being validated. However, I am still not getting a successful lock as indicated by R14 reads.

I forgot to mention. You have the the status_sel to DPLL R Divider by 2:

I have those status's set to LEDs, and the LEDs toggle from high to low. Remaining high for one second before going low. Also, remaining low for one second before going high.

Hope that helps diagnose the problem.

Hello,

We were able to achieve LOPL lock after waiting anywhere between 30mins to an hour. Additionally, the status pins are in phase with one another and R14 is reporting 0x00. Looks like everything is working just fine.

I do have a final question: Is there any way to speed up the LOPL lock time? 

I've marked this resolved. I greatly appreciate your help!!

Thanks,
Javier

Javier,

Thanks for the update.

With a narrow DPLL LBW ~0.01 Hz, the updates to the DPLL are very slow and take time which means updates to the APLL numerator are slow causing a long wait time for phase locking. This is typical behavior and cannot be sped up with 1-PPS inputs.

Regards,

Jennifer