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LMK04832EVM: EXIT HOLDOVER MODE

David Ferré
Prodigy 10 points
Part Number: LMK04832EVM
Other Parts Discussed in Thread: LMK04832

Hi ,

To understand how the LMK04832 works, we have the evaluation card that Ti offers. (VCXO 122.88 MHz)

 

I would like to use the LMK04832 in "holdover" mode and I would like a little more explanation on exiting this mode.

On the "pll1 holdover control" I select an exit mode "exit based on DLD"

I use an external 10MHz reference clock connected to CLKin1. (CLKin0 is not selected)

This reference clock may or may not be present.

In the absence (10MHz reference clock = OFF) of this clock, the LMK04832 switches to "Holdover" mode with a pre-established DAC voltage (CPout1).

On the other hand, when this reference clock returns, the LMK04832 remains in "holdover" mode, it does not want to lock onto this reference clock.

Can you explain this to me?

 

Second scenario, can we adjust the entry into "holdover" mode according to the frequency of the external clock.

I observe the operation by varying the frequency of the external reference clock 10MHz+350Hz and 10MHz-520Hz the PLL1 goes off (LD1 off)

The voltage on the VCXO follows the variation of the external clock frequency (the voltage on the VCXO is either 0 or +3.3V in this case).

On the other hand, when the PLL1 comes off I would like the LMK04832 to be able to switch to "holdvover" mode.

Is it possible ?

 

Attached is the Holdover_mode_exit_based_on_DLD.tcs file

Holdover_mode_exit_based_on_DLD.tcs

 

Thank you for the help provided.

Best regards

David

  • 0
    TI__Mastermind 29022 points

    Hi David, 
    Exiting holdover mode is dependent on how holdover mode was setup. 

    You can exit holdover mode based on two conditions. 1 which is when LOS_EN = 1 & the second condition is a wait condition where PLL1 R & N dividers are both phase aligned - this can take some time. 

    If you wish to reconnect to reference clk once available again please set CLKin_SEL_Manual =3 : 

    You can also have automatic holdover mode where a priority scheme exists on which clock to use as active reference: 

    Clkin0 has the highest priority. In your case given it's not enabled as a reference clock, as a matter of fact you only have CLKin1_EN set to high (which is correct) which results in CLKin1 having priority. 


    For your second question - yes LKM04832 can switch to holdover mode. As a matter of fact it holdover mode applies only to PLL1.
    Try changing HOLDER_EXIT_MODE = Exit Based on LOS: 

    Regards, 

    Vicente 

  • 0 in reply to vicente flores prado
    Prodigy 10 points

    Hi Vicente ,

    Thank you for this additional information.
    For the answer to the first question:
    After selecting CLKin_SEL_MANUAL = 3 (holdover) the LMK04832 exits holdover mode when a reference clock returns.
    In fact, it can take several seconds or even one to two minutes.
    This time is not constant.
    Is it possible to reduce this hanging time by adjusting the parameters HOLDOVER_DLD_CNT, PLL1_WND_SIZE...?
    If so can you give us the correct parameters to adjust.

    for the second question:
    I actually wanted to keep the operating mode of the first question, so I selected HOLDOVER_VTUNE_DET with
    DAC voltages between 1.6V and 2.11V. I was able to see that the LMK enters holdover mode when the frequency of the external reference clock (therefore CPout1) reaches the programmed voltages.
    On the other hand, when a viable reference clock returns, the LMK remains in holdover mode, there is no lock on the clock (even after several minutes)
    Can you explain this state to me?

    Attached is the file Holdover_DLD_track_vtune_det1.tcs

    Holdover_DLD_track_vtune_det1.tcs

    Thank you again for your support
    Best regards
    David

  • 0 in reply to David Ferré
    TI__Mastermind 29022 points

    Hi David, 
    Yes, the parameters can be adjusted to exit holder over more quickly. Note these apply when Holdover exit is based on DLD which waits for phase alignment between PLL1 R & N dividers. This can take some time. 
    HOLDOVER_DLD_CNT must be reduced and so must PLL1_WND_SIZE. 

    Say for example we set holdover_DLD_CNT = 1 & PLL1_WND_SIZE = 9 ns

    If within this window, we had one 1 good clock cycle - the device will exit holdover mode. There is also a PPM requirement listed: 

    So in other words if your clock is within 720 ppm in this window - device will exit holdover mode. 

    In regards to your second question - if device goes under low trip or over high trip - holdover will be entered. As stated before please set HOLDOVER_EN = "Exit Based on LOS." LOS_EN must also be HIGH. 

    If you set holdover exit based on LOS - HOLDOVER_DLD_CNT & PLL1_WND_SIZE don't matter.