• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 22 subscribers
  • Views 497 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMX2595: About LD_DLY

user1656626
Prodigy 80 points

Part Number: LMX2595

Hi there,

It uses LMX2595.
If the OSC is disconnected while 15GHz is being output, MUXOUT will output that it is locked even though the RFOUT frequency lock is released. (High level)

When I checked the waveform with an oscilloscope, a pulse signal was being output. At this time, setting LD_DLY will reduce the pulse signal.
Also, the pulse signal decreases even if Fpd changes from 100MHz to 10MHz.

- Is there an appropriate LD_DLY value? Please tell me the recommended value when Fpd=100MHz,Fpd=10MHz.

The current settings are OSC=100MHz, Fpd=10MHz, Fout=15GHz, LD_DLY=0, lock detect type=1.

  • 0
    TI__Guru** 121240 points

    Hi There,

    We can configure LD to "VCOCal" or "Vtuen and VCOCal". After a VCO calibration is complete and the LD_DLY counter is time out, VCOCal will assert HIGH. In other words, LD_DLY will only affect the response time of the LD. 

    If you do not care the LD response time, you can set LD_DLY to a vey large number.

    To get better pll performance, we should use higher fpd frequency. Since you have a 100MHz input, I would use fpd=100MHz as well. Set LD_DLY to a larger number to overcome false LD issue.

    Does your application require removing the OSCin signal? What is the forma of your input signal, differential or single-ended?

  • 0 in reply to Noel Fung
    Prodigy 80 points

    Hi There,

    Thank you for answering.

    The input signal format is single-ended.
    I am monitoring the LD output and need to display the LD correctly.
    Locked = high level, unlocked = low level.

    It incorrectly recognizes the unlocking as a pulse signal and displays "Locked".

    Is the LD of LMX2595 analog? Do I need an external filter to remove the rise?

  • +1 in reply to user1656626
    TI__Guru** 121240 points

    Hi There,

    Even if LD_DLY = a big number, you will get correct digital LD output in response to the VCO lock status, it just take a little bit longer response time.

    The problem you are seeing is likely due to noise going into OSCin when the reference clock is removed. As a result, the output of OSCin is toggling and the phase detector thinks input clock still exist.