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LMK03328: frequency change sequence and output stabilization time

Yoonsun Kim
Expert 1870 points

Part Number: LMK03328

Hi,

My system is required dynamic output frequency change function. The input reference clock is fixed.

When I checked TICS Pro - Configuration Wizard, I saw 'score' on bottom yellow box.

1> How does TICS Pro measure score? Which one is the highest score? 0 or 100?

2> What is the best sequence for finding high scoring divider numbers?

3> Is the any order to write registers when changing output frequency?

4> After writing last register, how long does it take for output to be stabilized?

Regards,

YS

  • 0
    TI__Mastermind 23280 points

    YS,

    Score is primarily based on the VCO frequency - generally, the lower the VCO frequency, the higher the score:

    Using a fractional PLL rather than an integer divide also impacts the score:

    The final score is also impacted by crosstalk between the two VCOs if both PLLs are used.

    TICS Pro will automatically select the solution with the highest score.

    See this except from the datasheet for changing the output by only changing the channel divider:

    If changing the PLL settings is required, then after configuring the PLL settings, toggle PLLx_PDN from '0' to '1' to '0' to recalibrate the PLL with the new settings. If recalibrating the PLL is required, then refer to this table for the timing estimate:

    Thanks,

    Kadeem