Part Number: CDCE6214
Other Parts Discussed in Thread: DS160PT801, , LMK5B33216
Hello TI Team,
Can I connect 100Mhz LVDS clock at PRIREF_P/N (Pin 5 and 6 ) CDCE6214WRGERQ1 to Generate HCSL clock?
LVDS voltage swing at PRIREF_P/N (Pin 5 and 6 ) is 350mVpp to 410mVpp.
Thanks and Regards,
Prashanth Pai B
Prashanth,
The swing on the input clock must not be lower than the datasheet minimum of 0.4 V differential:
If this criteria is met, there is no issue using a 100-MHz LVDS clock - the input and isolation data is collected using one:
Thanks,
Kadeem
Thanks for the reply, We have PLL with HCSL output and will connect this to REFCLK of Retimer DS160PT801 chip.
Below is the Query.Below pasted proposed clock routing in our Board FYR.
1.Is clock propagation delay(PCB) of clock from SI5518 to DS160PT801 will effect the performance ?
2.If yes, Can we tune/adjust this in DS160PT801
